uart_top.tan.qmsg

Uart port 是一段不错的

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "15 " "Warning: Found 15 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~32 " "Info: Detected gated clock \"uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~32\" as buffer" {  } { { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 32 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~32" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[0\] " "Info: Detected ripple clock \"uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[0\]\" as buffer" {  } { { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 42 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[1\] " "Info: Detected ripple clock \"uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[1\]\" as buffer" {  } { { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 42 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[2\] " "Info: Detected ripple clock \"uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[2\]\" as buffer" {  } { { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 42 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[7\] " "Info: Detected ripple clock \"uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[7\]\" as buffer" {  } { { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 42 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~30 " "Info: Detected gated clock \"uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~30\" as buffer" {  } { { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 32 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~30" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[3\] " "Info: Detected ripple clock \"uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[3\]\" as buffer" {  } { { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 42 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[6\] " "Info: Detected ripple clock \"uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[6\]\" as buffer" {  } { { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 42 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[4\] " "Info: Detected ripple clock \"uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[4\]\" as buffer" {  } { { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 42 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart_clk:uart_clk_gen_a\|divide_by_13:divide_13\|temp\[3\] " "Info: Detected ripple clock \"uart_clk:uart_clk_gen_a\|divide_by_13:divide_13\|temp\[3\]\" as buffer" {  } { { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 24 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "uart_clk:uart_clk_gen_a\|divide_by_13:divide_13\|temp\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[5\] " "Info: Detected ripple clock \"uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[5\]\" as buffer" {  } { { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 42 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~31 " "Info: Detected gated clock \"uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~31\" as buffer" {  } { { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 32 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~31" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~33 " "Info: Detected gated clock \"uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~33\" as buffer" {  } { { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 32 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~33" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~34 " "Info: Detected gated clock \"uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~34\" as buffer" {  } { { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 32 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~34" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp0\[2\] " "Info: Detected ripple clock \"uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp0\[2\]\" as buffer" {  } { { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 60 -1 0 } } { "d:/program files/alter/bin/Assignment Editor.qase" "" { Assignment "d:/program files/alter/bin/Assignment Editor.qase" 1 { { 0 "uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp0\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sys_clock register uart_emitter:uart_emitter_a\|serial register uart_receive:uart_receiver_a\|bus\[5\] 115.17 MHz 8.683 ns Internal " "Info: Clock \"sys_clock\" has Internal fmax of 115.17 MHz between source register \"uart_emitter:uart_emitter_a\|serial\" and destination register \"uart_receive:uart_receiver_a\|bus\[5\]\" (period= 8.683 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.364 ns + Longest register register " "Info: + Longest register to register delay is 2.364 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns uart_emitter:uart_emitter_a\|serial 1 REG LC10_7_E2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC10_7_E2; Fanout = 11; REG Node = 'uart_emitter:uart_emitter_a\|serial'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { uart_emitter:uart_emitter_a|serial } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.090 ns) + CELL(0.358 ns) 1.609 ns uart_receive:uart_receiver_a\|bus\[0\]~15 2 COMB LC9_5_E2 8 " "Info: 2: + IC(1.090 ns) + CELL(0.358 ns) = 1.609 ns; Loc. = LC9_5_E2; Fanout = 8; COMB Node = 'uart_receive:uart_receiver_a\|bus\[0\]~15'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.448 ns" { uart_emitter:uart_emitter_a|serial uart_receive:uart_receiver_a|bus[0]~15 } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.509 ns) 2.364 ns uart_receive:uart_receiver_a\|bus\[5\] 3 REG LC10_5_E2 1 " "Info: 3: + IC(0.246 ns) + CELL(0.509 ns) = 2.364 ns; Loc. = LC10_5_E2; Fanout = 1; REG Node = 'uart_receive:uart_receiver_a\|bus\[5\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.755 ns" { uart_receive:uart_receiver_a|bus[0]~15 uart_receive:uart_receiver_a|bus[5] } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.028 ns ( 43.49 % ) " "Info: Total cell delay = 1.028 ns ( 43.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.336 ns ( 56.51 % ) " "Info: Total interconnect delay = 1.336 ns ( 56.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "2.364 ns" { uart_emitter:uart_emitter_a|serial uart_receive:uart_receiver_a|bus[0]~15 uart_receive:uart_receiver_a|bus[5] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "2.364 ns" { uart_emitter:uart_emitter_a|serial uart_receive:uart_receiver_a|bus[0]~15 uart_receive:uart_receiver_a|bus[5] } { 0.000ns 1.090ns 0.246ns } { 0.161ns 0.358ns 0.509ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.786 ns - Smallest " "Info: - Smallest clock skew is -5.786 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clock destination 11.100 ns + Shortest register " "Info: + Shortest clock path from clock \"sys_clock\" to destination register is 11.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns sys_clock 1 CLK PIN_95 4 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 4; CLK Node = 'sys_clock'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { sys_clock } "NODE_NAME" } "" } } { "uart_top.v" "" { Text "E:/verilog/uart/uart_top.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.778 ns) + CELL(0.496 ns) 2.164 ns uart_clk:uart_clk_gen_a\|divide_by_13:divide_13\|temp\[3\] 2 REG LC6_1_F2 11 " "Info: 2: + IC(0.778 ns) + CELL(0.496 ns) = 2.164 ns; Loc. = LC6_1_F2; Fanout = 11; REG Node = 'uart_clk:uart_clk_gen_a\|divide_by_13:divide_13\|temp\[3\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.274 ns" { sys_clock uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[3] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.505 ns) + CELL(0.496 ns) 6.165 ns uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[5\] 3 REG LC7_1_D1 3 " "Info: 3: + IC(3.505 ns) + CELL(0.496 ns) = 6.165 ns; Loc. = LC7_1_D1; Fanout = 3; REG Node = 'uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[5\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "4.001 ns" { uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[3] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[5] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.798 ns) 7.268 ns uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~31 4 COMB LC1_2_D1 1 " "Info: 4: + IC(0.305 ns) + CELL(0.798 ns) = 7.268 ns; Loc. = LC1_2_D1; Fanout = 1; COMB Node = 'uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~31'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.103 ns" { uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[5] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~31 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.288 ns) + CELL(0.358 ns) 7.914 ns uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~34 5 COMB LC10_1_D1 30 " "Info: 5: + IC(0.288 ns) + CELL(0.358 ns) = 7.914 ns; Loc. = LC10_1_D1; Fanout = 30; COMB Node = 'uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~34'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.646 ns" { uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~31 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.186 ns) + CELL(0.000 ns) 11.100 ns uart_receive:uart_receiver_a\|bus\[5\] 6 REG LC10_5_E2 1 " "Info: 6: + IC(3.186 ns) + CELL(0.000 ns) = 11.100 ns; Loc. = LC10_5_E2; Fanout = 1; REG Node = 'uart_receive:uart_receiver_a\|bus\[5\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "3.186 ns" { uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_receive:uart_receiver_a|bus[5] } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.038 ns ( 27.37 % ) " "Info: Total cell delay = 3.038 ns ( 27.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.062 ns ( 72.63 % ) " "Info: Total interconnect delay = 8.062 ns ( 72.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "11.100 ns" { sys_clock uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[3] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[5] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~31 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_receive:uart_receiver_a|bus[5] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "11.100 ns" { sys_clock sys_clock~out0 uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[3] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[5] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~31 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_receive:uart_receiver_a|bus[5] } { 0.000ns 0.000ns 0.778ns 3.505ns 0.305ns 0.288ns 3.186ns } { 0.000ns 0.890ns 0.496ns 0.496ns 0.798ns 0.358ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clock source 16.886 ns - Longest register " "Info: - Longest clock path from clock \"sys_clock\" to source register is 16.886 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns sys_clock 1 CLK PIN_95 4 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 4; CLK Node = 'sys_clock'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { sys_clock } "NODE_NAME" } "" } } { "uart_top.v" "" { Text "E:/verilog/uart/uart_top.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.778 ns) + CELL(0.496 ns) 2.164 ns uart_clk:uart_clk_gen_a\|divide_by_13:divide_13\|temp\[3\] 2 REG LC6_1_F2 11 " "Info: 2: + IC(0.778 ns) + CELL(0.496 ns) = 2.164 ns; Loc. = LC6_1_F2; Fanout = 11; REG Node = 'uart_clk:uart_clk_gen_a\|divide_by_13:divide_13\|temp\[3\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.274 ns" { sys_clock uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[3] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.505 ns) + CELL(0.496 ns) 6.165 ns uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[1\] 3 REG LC3_1_D1 3 " "Info: 3: + IC(3.505 ns) + CELL(0.496 ns) = 6.165 ns; Loc. = LC3_1_D1; Fanout = 3; REG Node = 'uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp\[1\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "4.001 ns" { uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[3] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[1] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.298 ns) + CELL(0.890 ns) 7.353 ns uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~32 4 COMB LC7_2_D1 1 " "Info: 4: + IC(0.298 ns) + CELL(0.890 ns) = 7.353 ns; Loc. = LC7_2_D1; Fanout = 1; COMB Node = 'uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~32'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.188 ns" { uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[1] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.358 ns) 7.957 ns uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~33 5 COMB LC10_2_D1 1 " "Info: 5: + IC(0.246 ns) + CELL(0.358 ns) = 7.957 ns; Loc. = LC10_2_D1; Fanout = 1; COMB Node = 'uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~33'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.604 ns" { uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.260 ns) + CELL(0.879 ns) 9.096 ns uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~34 6 COMB LC10_1_D1 30 " "Info: 6: + IC(0.260 ns) + CELL(0.879 ns) = 9.096 ns; Loc. = LC10_1_D1; Fanout = 30; COMB Node = 'uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|clock~34'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.139 ns" { uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.216 ns) + CELL(0.496 ns) 12.808 ns uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp0\[2\] 7 REG LC5_2_E1 24 " "Info: 7: + IC(3.216 ns) + CELL(0.496 ns) = 12.808 ns; Loc. = LC5_2_E1; Fanout = 24; REG Node = 'uart_clk:uart_clk_gen_a\|divide_by_256:divide_256\|temp0\[2\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "3.712 ns" { uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[2] } "NODE_NAME" } "" } } { "uart_clk.v" "" { Text "E:/verilog/uart/uart_clk.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.078 ns) + CELL(0.000 ns) 16.886 ns uart_emitter:uart_emitter_a\|serial 8 REG LC10_7_E2 11 " "Info: 8: + IC(4.078 ns) + CELL(0.000 ns) = 16.886 ns; Loc. = LC10_7_E2; Fanout = 11; REG Node = 'uart_emitter:uart_emitter_a\|serial'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "4.078 ns" { uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[2] uart_emitter:uart_emitter_a|serial } "NODE_NAME" } "" } } { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.505 ns ( 26.68 % ) " "Info: Total cell delay = 4.505 ns ( 26.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.381 ns ( 73.32 % ) " "Info: Total interconnect delay = 12.381 ns ( 73.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "16.886 ns" { sys_clock uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[3] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[1] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[2] uart_emitter:uart_emitter_a|serial } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "16.886 ns" { sys_clock sys_clock~out0 uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[3] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[1] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[2] uart_emitter:uart_emitter_a|serial } { 0.000ns 0.000ns 0.778ns 3.505ns 0.298ns 0.246ns 0.260ns 3.216ns 4.078ns } { 0.000ns 0.890ns 0.496ns 0.496ns 0.890ns 0.358ns 0.879ns 0.496ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "11.100 ns" { sys_clock uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[3] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[5] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~31 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_receive:uart_receiver_a|bus[5] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "11.100 ns" { sys_clock sys_clock~out0 uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[3] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[5] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~31 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_receive:uart_receiver_a|bus[5] } { 0.000ns 0.000ns 0.778ns 3.505ns 0.305ns 0.288ns 3.186ns } { 0.000ns 0.890ns 0.496ns 0.496ns 0.798ns 0.358ns 0.000ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "16.886 ns" { sys_clock uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[3] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[1] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[2] uart_emitter:uart_emitter_a|serial } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "16.886 ns" { sys_clock sys_clock~out0 uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[3] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[1] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[2] uart_emitter:uart_emitter_a|serial } { 0.000ns 0.000ns 0.778ns 3.505ns 0.298ns 0.246ns 0.260ns 3.216ns 4.078ns } { 0.000ns 0.890ns 0.496ns 0.496ns 0.890ns 0.358ns 0.879ns 0.496ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "Info: + Micro clock to output delay of source is 0.335 ns" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 5 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.198 ns + " "Info: + Micro setup delay of destination is 0.198 ns" {  } { { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "2.364 ns" { uart_emitter:uart_emitter_a|serial uart_receive:uart_receiver_a|bus[0]~15 uart_receive:uart_receiver_a|bus[5] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "2.364 ns" { uart_emitter:uart_emitter_a|serial uart_receive:uart_receiver_a|bus[0]~15 uart_receive:uart_receiver_a|bus[5] } { 0.000ns 1.090ns 0.246ns } { 0.161ns 0.358ns 0.509ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "11.100 ns" { sys_clock uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[3] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[5] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~31 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_receive:uart_receiver_a|bus[5] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "11.100 ns" { sys_clock sys_clock~out0 uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[3] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[5] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~31 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_receive:uart_receiver_a|bus[5] } { 0.000ns 0.000ns 0.778ns 3.505ns 0.305ns 0.288ns 3.186ns } { 0.000ns 0.890ns 0.496ns 0.496ns 0.798ns 0.358ns 0.000ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_top" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_top.quartus_db" { Floorplan "E:/verilog/uart/" "" "16.886 ns" { sys_clock uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[3] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[1] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[2] uart_emitter:uart_emitter_a|serial } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "16.886 ns" { sys_clock sys_clock~out0 uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[3] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[1] uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[2] uart_emitter:uart_emitter_a|serial } { 0.000ns 0.000ns 0.778ns 3.505ns 0.298ns 0.246ns 0.260ns 3.216ns 4.078ns } { 0.000ns 0.890ns 0.496ns 0.496ns 0.890ns 0.358ns 0.879ns 0.496ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}