usrt_receive.hier_info

来自「Uart port 是一段不错的」· HIER_INFO 代码 · 共 100 行

|usrt_receive
read_not_ready_out <= read_not_ready_out~1.DB_MAX_OUTPUT_PORT_TYPE
clr_sample_counter <= Select~0.DB_MAX_OUTPUT_PORT_TYPE
bit_counter[0] <= bit_counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bit_counter[1] <= bit_counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bit_counter[2] <= bit_counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
bit_counter[3] <= bit_counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sample_counter[0] <= sample_counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sample_counter[1] <= sample_counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sample_counter[2] <= sample_counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sample_counter[3] <= sample_counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rcv_shiftreg[0] <= rcv_shiftreg[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rcv_shiftreg[1] <= rcv_shiftreg[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rcv_shiftreg[2] <= rcv_shiftreg[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rcv_shiftreg[3] <= rcv_shiftreg[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rcv_shiftreg[4] <= rcv_shiftreg[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rcv_shiftreg[5] <= rcv_shiftreg[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rcv_shiftreg[6] <= rcv_shiftreg[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rcv_shiftreg[7] <= rcv_shiftreg[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
inc_sample_counter <= Select~1.DB_MAX_OUTPUT_PORT_TYPE
clr_bit_counter <= clr_bit_counter~0.DB_MAX_OUTPUT_PORT_TYPE
date_bus[0] <= date_bus[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
date_bus[1] <= date_bus[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
date_bus[2] <= date_bus[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
date_bus[3] <= date_bus[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
date_bus[4] <= date_bus[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
date_bus[5] <= date_bus[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
date_bus[6] <= date_bus[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
date_bus[7] <= date_bus[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
inc_bit_counter <= inc_bit_counter~1.DB_MAX_OUTPUT_PORT_TYPE
shift <= shift~0.DB_MAX_OUTPUT_PORT_TYPE
load <= load~3.DB_MAX_OUTPUT_PORT_TYPE
error1 <= error1~2.DB_MAX_OUTPUT_PORT_TYPE
error2 <= error2~3.DB_MAX_OUTPUT_PORT_TYPE
serial => clr_sample_counter~0.OUTPUTSELECT
serial => next_state~3.OUTPUTSELECT
serial => next_state~4.OUTPUTSELECT
serial => next_state~5.OUTPUTSELECT
serial => inc_sample_counter~0.OUTPUTSELECT
serial => load~0.DATAA
serial => next_state.idle.IN2
serial => error2~0.DATAA
serial => next_state.starting.IN1
serial => rcv_shiftreg[7]~reg0.DATAIN
read_not_ready_in => error1~0.DATAB
read_not_ready_in => load~0.OUTPUTSELECT
read_not_ready_in => error2~0.OUTPUTSELECT
rest => sample_counter[3]~reg0.ACLR
rest => sample_counter[2]~reg0.ACLR
rest => sample_counter[1]~reg0.ACLR
rest => sample_counter[0]~reg0.ACLR
rest => rcv_shiftreg[7]~reg0.ACLR
rest => rcv_shiftreg[6]~reg0.ACLR
rest => rcv_shiftreg[5]~reg0.ACLR
rest => rcv_shiftreg[4]~reg0.ACLR
rest => rcv_shiftreg[3]~reg0.ACLR
rest => rcv_shiftreg[2]~reg0.ACLR
rest => rcv_shiftreg[1]~reg0.ACLR
rest => rcv_shiftreg[0]~reg0.ACLR
rest => bit_counter[3]~reg0.ACLR
rest => bit_counter[2]~reg0.ACLR
rest => bit_counter[1]~reg0.ACLR
rest => bit_counter[0]~reg0.ACLR
rest => date_bus[7]~reg0.ACLR
rest => date_bus[6]~reg0.ACLR
rest => date_bus[5]~reg0.ACLR
rest => date_bus[4]~reg0.ACLR
rest => date_bus[3]~reg0.ACLR
rest => date_bus[2]~reg0.ACLR
rest => date_bus[1]~reg0.ACLR
rest => date_bus[0]~reg0.ACLR
rest => state~1.IN1
clk => sample_counter[3]~reg0.CLK
clk => sample_counter[2]~reg0.CLK
clk => sample_counter[1]~reg0.CLK
clk => sample_counter[0]~reg0.CLK
clk => rcv_shiftreg[7]~reg0.CLK
clk => rcv_shiftreg[6]~reg0.CLK
clk => rcv_shiftreg[5]~reg0.CLK
clk => rcv_shiftreg[4]~reg0.CLK
clk => rcv_shiftreg[3]~reg0.CLK
clk => rcv_shiftreg[2]~reg0.CLK
clk => rcv_shiftreg[1]~reg0.CLK
clk => rcv_shiftreg[0]~reg0.CLK
clk => bit_counter[3]~reg0.CLK
clk => bit_counter[2]~reg0.CLK
clk => bit_counter[1]~reg0.CLK
clk => bit_counter[0]~reg0.CLK
clk => date_bus[7]~reg0.CLK
clk => date_bus[6]~reg0.CLK
clk => date_bus[5]~reg0.CLK
clk => date_bus[4]~reg0.CLK
clk => date_bus[3]~reg0.CLK
clk => date_bus[2]~reg0.CLK
clk => date_bus[1]~reg0.CLK
clk => date_bus[0]~reg0.CLK
clk => state~0.IN1