uart_receive.tan.qmsg

来自「Uart port 是一段不错的」· QMSG 代码 · 共 12 行 · 第 1/3 页

{ "Info" "ITDB_FULL_TCO_RESULT" "clk counter\[3\] counter\[3\]~reg0 6.834 ns register " "Info: tco from clock \"clk\" to destination pin \"counter\[3\]\" through register \"counter\[3\]~reg0\" is 6.834 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.673 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 1.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clk 1 CLK PIN_95 26 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 26; CLK Node = 'clk'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { clk } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.000 ns) 1.673 ns counter\[3\]~reg0 2 REG LC4_6_A2 4 " "Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC4_6_A2; Fanout = 4; REG Node = 'counter\[3\]~reg0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.783 ns" { clk counter[3]~reg0 } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.20 % ) " "Info: Total cell delay = 0.890 ns ( 53.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns ( 46.80 % ) " "Info: Total interconnect delay = 0.783 ns ( 46.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.673 ns" { clk counter[3]~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.673 ns" { clk clk~out0 counter[3]~reg0 } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "Info: + Micro clock to output delay of source is 0.335 ns" {  } { { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.826 ns + Longest register pin " "Info: + Longest register to pin delay is 4.826 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns counter\[3\]~reg0 1 REG LC4_6_A2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC4_6_A2; Fanout = 4; REG Node = 'counter\[3\]~reg0'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { counter[3]~reg0 } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.255 ns) + CELL(2.410 ns) 4.826 ns counter\[3\] 2 PIN PIN_103 0 " "Info: 2: + IC(2.255 ns) + CELL(2.410 ns) = 4.826 ns; Loc. = PIN_103; Fanout = 0; PIN Node = 'counter\[3\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "4.665 ns" { counter[3]~reg0 counter[3] } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.571 ns ( 53.27 % ) " "Info: Total cell delay = 2.571 ns ( 53.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.255 ns ( 46.73 % ) " "Info: Total interconnect delay = 2.255 ns ( 46.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "4.826 ns" { counter[3]~reg0 counter[3] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "4.826 ns" { counter[3]~reg0 counter[3] } { 0.000ns 2.255ns } { 0.161ns 2.410ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.673 ns" { clk counter[3]~reg0 } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.673 ns" { clk clk~out0 counter[3]~reg0 } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "4.826 ns" { counter[3]~reg0 counter[3] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "4.826 ns" { counter[3]~reg0 counter[3] } { 0.000ns 2.255ns } { 0.161ns 2.410ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "bus_reg\[0\] rest clk -1.716 ns register " "Info: th for register \"bus_reg\[0\]\" (data pin = \"rest\", clock pin = \"clk\") is -1.716 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.673 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 1.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clk 1 CLK PIN_95 26 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 26; CLK Node = 'clk'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { clk } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.000 ns) 1.673 ns bus_reg\[0\] 2 REG LC8_4_A2 1 " "Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC8_4_A2; Fanout = 1; REG Node = 'bus_reg\[0\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.783 ns" { clk bus_reg[0] } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.20 % ) " "Info: Total cell delay = 0.890 ns ( 53.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns ( 46.80 % ) " "Info: Total interconnect delay = 0.783 ns ( 46.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.673 ns" { clk bus_reg[0] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.673 ns" { clk clk~out0 bus_reg[0] } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.364 ns + " "Info: + Micro hold delay of destination is 0.364 ns" {  } { { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.753 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.753 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.960 ns) 0.960 ns rest 1 PIN PIN_127 12 " "Info: 1: + IC(0.000 ns) + CELL(0.960 ns) = 0.960 ns; Loc. = PIN_127; Fanout = 12; PIN Node = 'rest'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "" { rest } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.131 ns) + CELL(0.879 ns) 2.970 ns bus_reg\[0\]~71 2 COMB LC4_4_A2 8 " "Info: 2: + IC(1.131 ns) + CELL(0.879 ns) = 2.970 ns; Loc. = LC4_4_A2; Fanout = 8; COMB Node = 'bus_reg\[0\]~71'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "2.010 ns" { rest bus_reg[0]~71 } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.274 ns) + CELL(0.509 ns) 3.753 ns bus_reg\[0\] 3 REG LC8_4_A2 1 " "Info: 3: + IC(0.274 ns) + CELL(0.509 ns) = 3.753 ns; Loc. = LC8_4_A2; Fanout = 1; REG Node = 'bus_reg\[0\]'" {  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "0.783 ns" { bus_reg[0]~71 bus_reg[0] } "NODE_NAME" } "" } } { "uart_receive.v" "" { Text "E:/verilog/uart/uart_receive.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.348 ns ( 62.56 % ) " "Info: Total cell delay = 2.348 ns ( 62.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.405 ns ( 37.44 % ) " "Info: Total interconnect delay = 1.405 ns ( 37.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "3.753 ns" { rest bus_reg[0]~71 bus_reg[0] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "3.753 ns" { rest rest~out0 bus_reg[0]~71 bus_reg[0] } { 0.000ns 0.000ns 1.131ns 0.274ns } { 0.000ns 0.960ns 0.879ns 0.509ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "1.673 ns" { clk bus_reg[0] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "1.673 ns" { clk clk~out0 bus_reg[0] } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } } } { "d:/program files/alter/bin/Report_Window_01.qrpt" "" { Report "d:/program files/alter/bin/Report_Window_01.qrpt" "Compiler" "uart_receive" "UNKNOWN" "V1" "E:/verilog/uart/db/uart_receive.quartus_db" { Floorplan "E:/verilog/uart/" "" "3.753 ns" { rest bus_reg[0]~71 bus_reg[0] } "NODE_NAME" } "" } } { "d:/program files/alter/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/alter/bin/Technology_Viewer.qrui" "3.753 ns" { rest rest~out0 bus_reg[0]~71 bus_reg[0] } { 0.000ns 0.000ns 1.131ns 0.274ns } { 0.000ns 0.960ns 0.879ns 0.509ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 12 00:30:41 2006 " "Info: Processing ended: Tue Dec 12 00:30:41 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}