uart_clk.tan.rpt

来自「Uart port 是一段不错的」· RPT 代码 · 共 475 行 · 第 1/5 页

    Info: + Micro clock to output delay of source is 0.603 ns
    Info: + Micro setup delay of destination is 0.170 ns
Info: Clock "sel_baud_rate[0]" has Internal fmax of 161.32 MHz between source register "divide_by_256:divide_256|temp0[2]" and destination register "divide_by_256:divide_256|temp0[2]" (period= 6.199 ns)
    Info: + Longest register to register delay is 1.877 ns
        Info: 1: + IC(0.000 ns) + CELL(0.291 ns) = 0.291 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256|temp0[2]'
        Info: 2: + IC(0.321 ns) + CELL(1.265 ns) = 1.877 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256|temp0[2]'
        Info: Total cell delay = 1.556 ns ( 82.90 % )
        Info: Total interconnect delay = 0.321 ns ( 17.10 % )
    Info: - Smallest clock skew is -3.549 ns
        Info: + Shortest clock path from clock "sel_baud_rate[0]" to destination register is 13.161 ns
            Info: 1: + IC(0.000 ns) + CELL(1.845 ns) = 1.845 ns; Loc. = PIN_138; Fanout = 3; CLK Node = 'sel_baud_rate[0]'
            Info: 2: + IC(3.483 ns) + CELL(0.645 ns) = 5.973 ns; Loc. = LC3_5_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256|clock~31'
            Info: 3: + IC(0.321 ns) + CELL(0.645 ns) = 6.939 ns; Loc. = LC5_5_O1; Fanout = 4; COMB Node = 'divide_by_256:divide_256|clock~34'
            Info: 4: + IC(6.222 ns) + CELL(0.000 ns) = 13.161 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256|temp0[2]'
            Info: Total cell delay = 3.135 ns ( 23.82 % )
            Info: Total interconnect delay = 10.026 ns ( 76.18 % )
        Info: - Longest clock path from clock "sel_baud_rate[0]" to source register is 16.710 ns
            Info: 1: + IC(0.000 ns) + CELL(1.845 ns) = 1.845 ns; Loc. = PIN_138; Fanout = 3; CLK Node = 'sel_baud_rate[0]'
            Info: 2: + IC(3.363 ns) + CELL(1.436 ns) = 6.644 ns; Loc. = LC10_4_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256|clock~30'
            Info: 3: + IC(1.297 ns) + CELL(1.581 ns) = 9.522 ns; Loc. = LC3_5_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256|clock~31'
            Info: 4: + IC(0.321 ns) + CELL(0.645 ns) = 10.488 ns; Loc. = LC5_5_O1; Fanout = 4; COMB Node = 'divide_by_256:divide_256|clock~34'
            Info: 5: + IC(6.222 ns) + CELL(0.000 ns) = 16.710 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256|temp0[2]'
            Info: Total cell delay = 5.507 ns ( 32.96 % )
            Info: Total interconnect delay = 11.203 ns ( 67.04 % )
    Info: + Micro clock to output delay of source is 0.603 ns
    Info: + Micro setup delay of destination is 0.170 ns
Warning: Circuit may not operate. Detected 6 non-operational path(s) clocked by clock "sys_clock" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "divide_by_256:divide_256|temp0[0]" and destination pin or register "divide_by_256:divide_256|temp0[1]" for clock "sys_clock" (Hold time is 1.862 ns)
    Info: + Largest clock skew is 3.041 ns
        Info: + Longest clock path from clock "sys_clock" to destination register is 19.557 ns
            Info: 1: + IC(0.000 ns) + CELL(1.451 ns) = 1.451 ns; Loc. = PIN_154; Fanout = 4; CLK Node = 'sys_clock'
            Info: 2: + IC(1.491 ns) + CELL(0.894 ns) = 3.836 ns; Loc. = LC5_16_N1; Fanout = 11; REG Node = 'divide_by_13:divide_13|temp[3]'
            Info: 3: + IC(2.783 ns) + CELL(0.894 ns) = 7.513 ns; Loc. = LC7_4_O1; Fanout = 3; REG Node = 'divide_by_256:divide_256|temp[6]'
            Info: 4: + IC(0.397 ns) + CELL(1.581 ns) = 9.491 ns; Loc. = LC10_4_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256|clock~30'
            Info: 5: + IC(1.297 ns) + CELL(1.581 ns) = 12.369 ns; Loc. = LC3_5_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256|clock~31'
            Info: 6: + IC(0.321 ns) + CELL(0.645 ns) = 13.335 ns; Loc. = LC5_5_O1; Fanout = 4; COMB Node = 'divide_by_256:divide_256|clock~34'
            Info: 7: + IC(6.222 ns) + CELL(0.000 ns) = 19.557 ns; Loc. = LC6_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256|temp0[1]'
            Info: Total cell delay = 7.046 ns ( 36.03 % )
            Info: Total interconnect delay = 12.511 ns ( 63.97 % )
        Info: - Shortest clock path from clock "sys_clock" to source register is 16.516 ns
            Info: 1: + IC(0.000 ns) + CELL(1.451 ns) = 1.451 ns; Loc. = PIN_154; Fanout = 4; CLK Node = 'sys_clock'
            Info: 2: + IC(1.491 ns) + CELL(0.894 ns) = 3.836 ns; Loc. = LC5_16_N1; Fanout = 11; REG Node = 'divide_by_13:divide_13|temp[3]'
            Info: 3: + IC(2.783 ns) + CELL(0.894 ns) = 7.513 ns; Loc. = LC3_4_O1; Fanout = 3; REG Node = 'divide_by_256:divide_256|temp[2]'
            Info: 4: + IC(0.379 ns) + CELL(0.645 ns) = 8.537 ns; Loc. = LC9_4_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256|clock~33'
            Info: 5: + IC(0.321 ns) + CELL(1.436 ns) = 10.294 ns; Loc. = LC5_5_O1; Fanout = 4; COMB Node = 'divide_by_256:divide_256|clock~34'
            Info: 6: + IC(6.222 ns) + CELL(0.000 ns) = 16.516 ns; Loc. = LC3_15_Z2; Fanout = 3; REG Node = 'divide_by_256:divide_256|temp0[0]'
            Info: Total cell delay = 5.320 ns ( 32.21 % )
            Info: Total interconnect delay = 11.196 ns ( 67.79 % )
    Info: - Micro clock to output delay of source is 0.603 ns
    Info: - Shortest register to register delay is 0.984 ns
        Info: 1: + IC(0.000 ns) + CELL(0.291 ns) = 0.291 ns; Loc. = LC3_15_Z2; Fanout = 3; REG Node = 'divide_by_256:divide_256|temp0[0]'
        Info: 2: + IC(0.365 ns) + CELL(0.328 ns) = 0.984 ns; Loc. = LC6_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256|temp0[1]'
        Info: Total cell delay = 0.619 ns ( 62.91 % )
        Info: Total interconnect delay = 0.365 ns ( 37.09 % )
    Info: + Micro hold delay of destination is 0.408 ns
Warning: Circuit may not operate. Detected 6 non-operational path(s) clocked by clock "sel_baud_rate[1]" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "divide_by_256:divide_256|temp0[0]" and destination pin or register "divide_by_256:divide_256|temp0[1]" for clock "sel_baud_rate[1]" (Hold time is 906 ps)
    Info: + Largest clock skew is 2.085 ns
        Info: + Longest clock path from clock "sel_baud_rate[1]" to destination register is 18.255 ns
            Info: 1: + IC(0.000 ns) + CELL(1.845 ns) = 1.845 ns; Loc. = PIN_131; Fanout = 3; CLK Node = 'sel_baud_rate[1]'
            Info: 2: + IC(4.742 ns) + CELL(1.602 ns) = 8.189 ns; Loc. = LC10_4_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256|clock~30'
            Info: 3: + IC(1.297 ns) + CELL(1.581 ns) = 11.067 ns; Loc. = LC3_5_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256|clock~31'
            Info: 4: + IC(0.321 ns) + CELL(0.645 ns) = 12.033 ns; Loc. = LC5_5_O1; Fanout = 4; COMB Node = 'divide_by_256:divide_256|clock~34'
            Info: 5: + IC(6.222 ns) + CELL(0.000 ns) = 18.255 ns; Loc. = LC6_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256|temp0[1]'
            Info: Total cell delay = 5.673 ns ( 31.08 % )
            Info: Total interconnect delay = 12.582 ns ( 68.92 % )
        Info: - Shortest clock path from clock "sel_baud_rate[1]" to source register is 16.170 ns
            Info: 1: + IC(0.000 ns) + CELL(1.845 ns) = 1.845 ns; Loc. = PIN_131; Fanout = 3; CLK Node = 'sel_baud_rate[1]'
            Info: 2: + IC(4.744 ns) + CELL(1.602 ns) = 8.191 ns; Loc. = LC9_4_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256|clock~33'
            Info: 3: + IC(0.321 ns) + CELL(1.436 ns) = 9.948 ns; Loc. = LC5_5_O1; Fanout = 4; COMB Node = 'divide_by_256:divide_256|clock~34'
            Info: 4: + IC(6.222 ns) + CELL(0.000 ns) = 16.170 ns; Loc. = LC3_15_Z2; Fanout = 3; REG Node = 'divide_by_256:divide_256|temp0[0]'
            Info: Total cell delay = 4.883 ns ( 30.20 % )
            Info: Total interconnect delay = 11.287 ns ( 69.80 % )
    Info: - Micro clock to output delay of source is 0.603 ns
    Info: - Shortest register to register delay is 0.984 ns
        Info: 1: + IC(0.000 ns) + CELL(0.291 ns) = 0.291 ns; Loc. = LC3_15_Z2; Fanout = 3; REG Node = 'divide_by_256:divide_256|temp0[0]'
        Info: 2: + IC(0.365 ns) + CELL(0.328 ns) = 0.984 ns; Loc. = LC6_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256|temp0[1]'
        Info: Total cell delay = 0.619 ns ( 62.91 % )
        Info: Total interconnect delay = 0.365 ns ( 37.09 % )
    Info: + Micro hold delay of destination is 0.408 ns
Warning: Circuit may not operate. Detected 6 non-operational path(s) clocked by clock "sel_baud_rate[0]" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "divide_by_256:divide_256|temp0[0]" and destination pin or register "divide_by_256:divide_256|temp0[1]" for clock "sel_baud_rate[0]" (Hold time is 2.37 ns)
    Info: + Largest clock skew is 3.549 ns
        Info: + Longest clock path from clock "sel_baud_rate[0]" to destination register is 16.710 ns
            Info: 1: + IC(0.000 ns) + CELL(1.845 ns) = 1.845 ns; Loc. = PIN_138; Fanout = 3; CLK Node = 'sel_baud_rate[0]'
            Info: 2: + IC(3.363 ns) + CELL(1.436 ns) = 6.644 ns; Loc. = LC10_4_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256|clock~30'
            Info: 3: + IC(1.297 ns) + CELL(1.581 ns) = 9.522 ns; Loc. = LC3_5_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256|clock~31'
            Info: 4: + IC(0.321 ns) + CELL(0.645 ns) = 10.488 ns; Loc. = LC5_5_O1; Fanout = 4; COMB Node = 'divide_by_256:divide_256|clock~34'
            Info: 5: + IC(6.222 ns) + CELL(0.000 ns) = 16.710 ns; Loc. = LC6_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256|temp0[1]'
            Info: Total cell delay = 5.507 ns ( 32.96 % )
            Info: Total interconnect delay = 11.203 ns ( 67.04 % )
        Info: - Shortest clock path from clock "sel_baud_rate[0]" to source register is 13.161 ns
            Info: 1: + IC(0.000 ns) + CELL(1.845 ns) = 1.845 ns; Loc. = PIN_138; Fanout = 3; CLK Node = 'sel_baud_rate[0]'
            Info: 2: + IC(3.483 ns) + CELL(0.645 ns) = 5.973 ns; Loc. = LC3_5_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256|clock~31'
            Info: 3: + IC(0.321 ns) + CELL(0.645 ns) = 6.939 ns; Loc. = LC5_5_O1; Fanout = 4; COMB Node = 'divide_by_256:divide_256|clock