uart_clk.tan.rpt

来自「Uart port 是一段不错的」· RPT 代码 · 共 475 行 · 第 1/5 页

Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off uart_clk -c uart_clk
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "sys_clock" is an undefined clock
    Info: Assuming node "sel_baud_rate[2]" is an undefined clock
    Info: Assuming node "sel_baud_rate[1]" is an undefined clock
    Info: Assuming node "sel_baud_rate[0]" is an undefined clock
Warning: Found 14 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "divide_by_256:divide_256|clock~34" as buffer
    Info: Detected gated clock "divide_by_256:divide_256|clock~33" as buffer
    Info: Detected gated clock "divide_by_256:divide_256|clock~32" as buffer
    Info: Detected ripple clock "divide_by_256:divide_256|temp[0]" as buffer
    Info: Detected ripple clock "divide_by_256:divide_256|temp[1]" as buffer
    Info: Detected ripple clock "divide_by_256:divide_256|temp[2]" as buffer
    Info: Detected gated clock "divide_by_256:divide_256|clock~31" as buffer
    Info: Detected ripple clock "divide_by_256:divide_256|temp[7]" as buffer
    Info: Detected gated clock "divide_by_256:divide_256|clock~30" as buffer
    Info: Detected ripple clock "divide_by_256:divide_256|temp[3]" as buffer
    Info: Detected ripple clock "divide_by_256:divide_256|temp[6]" as buffer
    Info: Detected ripple clock "divide_by_256:divide_256|temp[4]" as buffer
    Info: Detected ripple clock "divide_by_13:divide_13|temp[3]" as buffer
    Info: Detected ripple clock "divide_by_256:divide_256|temp[5]" as buffer
Info: Clock "sys_clock" has Internal fmax of 175.72 MHz between source register "divide_by_256:divide_256|temp0[2]" and destination register "divide_by_256:divide_256|temp0[2]" (period= 5.691 ns)
    Info: + Longest register to register delay is 1.877 ns
        Info: 1: + IC(0.000 ns) + CELL(0.291 ns) = 0.291 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256|temp0[2]'
        Info: 2: + IC(0.321 ns) + CELL(1.265 ns) = 1.877 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256|temp0[2]'
        Info: Total cell delay = 1.556 ns ( 82.90 % )
        Info: Total interconnect delay = 0.321 ns ( 17.10 % )
    Info: - Smallest clock skew is -3.041 ns
        Info: + Shortest clock path from clock "sys_clock" to destination register is 16.516 ns
            Info: 1: + IC(0.000 ns) + CELL(1.451 ns) = 1.451 ns; Loc. = PIN_154; Fanout = 4; CLK Node = 'sys_clock'
            Info: 2: + IC(1.491 ns) + CELL(0.894 ns) = 3.836 ns; Loc. = LC5_16_N1; Fanout = 11; REG Node = 'divide_by_13:divide_13|temp[3]'
            Info: 3: + IC(2.783 ns) + CELL(0.894 ns) = 7.513 ns; Loc. = LC3_4_O1; Fanout = 3; REG Node = 'divide_by_256:divide_256|temp[2]'
            Info: 4: + IC(0.379 ns) + CELL(0.645 ns) = 8.537 ns; Loc. = LC9_4_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256|clock~33'
            Info: 5: + IC(0.321 ns) + CELL(1.436 ns) = 10.294 ns; Loc. = LC5_5_O1; Fanout = 4; COMB Node = 'divide_by_256:divide_256|clock~34'
            Info: 6: + IC(6.222 ns) + CELL(0.000 ns) = 16.516 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256|temp0[2]'
            Info: Total cell delay = 5.320 ns ( 32.21 % )
            Info: Total interconnect delay = 11.196 ns ( 67.79 % )
        Info: - Longest clock path from clock "sys_clock" to source register is 19.557 ns
            Info: 1: + IC(0.000 ns) + CELL(1.451 ns) = 1.451 ns; Loc. = PIN_154; Fanout = 4; CLK Node = 'sys_clock'
            Info: 2: + IC(1.491 ns) + CELL(0.894 ns) = 3.836 ns; Loc. = LC5_16_N1; Fanout = 11; REG Node = 'divide_by_13:divide_13|temp[3]'
            Info: 3: + IC(2.783 ns) + CELL(0.894 ns) = 7.513 ns; Loc. = LC7_4_O1; Fanout = 3; REG Node = 'divide_by_256:divide_256|temp[6]'
            Info: 4: + IC(0.397 ns) + CELL(1.581 ns) = 9.491 ns; Loc. = LC10_4_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256|clock~30'
            Info: 5: + IC(1.297 ns) + CELL(1.581 ns) = 12.369 ns; Loc. = LC3_5_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256|clock~31'
            Info: 6: + IC(0.321 ns) + CELL(0.645 ns) = 13.335 ns; Loc. = LC5_5_O1; Fanout = 4; COMB Node = 'divide_by_256:divide_256|clock~34'
            Info: 7: + IC(6.222 ns) + CELL(0.000 ns) = 19.557 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256|temp0[2]'
            Info: Total cell delay = 7.046 ns ( 36.03 % )
            Info: Total interconnect delay = 12.511 ns ( 63.97 % )
    Info: + Micro clock to output delay of source is 0.603 ns
    Info: + Micro setup delay of destination is 0.170 ns
Info: Clock "sel_baud_rate[2]" Internal fmax is restricted to 220.99 MHz between source register "divide_by_256:divide_256|temp0[2]" and destination register "divide_by_256:divide_256|temp0[2]"
    Info: fmax restricted to clock pin edge rate 4.525 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.877 ns
            Info: 1: + IC(0.000 ns) + CELL(0.291 ns) = 0.291 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256|temp0[2]'
            Info: 2: + IC(0.321 ns) + CELL(1.265 ns) = 1.877 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256|temp0[2]'
            Info: Total cell delay = 1.556 ns ( 82.90 % )
            Info: Total interconnect delay = 0.321 ns ( 17.10 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "sel_baud_rate[2]" to destination register is 15.017 ns
                Info: 1: + IC(0.000 ns) + CELL(1.845 ns) = 1.845 ns; Loc. = PIN_37; Fanout = 1; CLK Node = 'sel_baud_rate[2]'
                Info: 2: + IC(5.369 ns) + CELL(1.581 ns) = 8.795 ns; Loc. = LC5_5_O1; Fanout = 4; COMB Node = 'divide_by_256:divide_256|clock~34'
                Info: 3: + IC(6.222 ns) + CELL(0.000 ns) = 15.017 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256|temp0[2]'
                Info: Total cell delay = 3.426 ns ( 22.81 % )
                Info: Total interconnect delay = 11.591 ns ( 77.19 % )
            Info: - Longest clock path from clock "sel_baud_rate[2]" to source register is 15.017 ns
                Info: 1: + IC(0.000 ns) + CELL(1.845 ns) = 1.845 ns; Loc. = PIN_37; Fanout = 1; CLK Node = 'sel_baud_rate[2]'
                Info: 2: + IC(5.369 ns) + CELL(1.581 ns) = 8.795 ns; Loc. = LC5_5_O1; Fanout = 4; COMB Node = 'divide_by_256:divide_256|clock~34'
                Info: 3: + IC(6.222 ns) + CELL(0.000 ns) = 15.017 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256|temp0[2]'
                Info: Total cell delay = 3.426 ns ( 22.81 % )
                Info: Total interconnect delay = 11.591 ns ( 77.19 % )
        Info: + Micro clock to output delay of source is 0.603 ns
        Info: + Micro setup delay of destination is 0.170 ns
Info: Clock "sel_baud_rate[1]" has Internal fmax of 211.19 MHz between source register "divide_by_256:divide_256|temp0[2]" and destination register "divide_by_256:divide_256|temp0[2]" (period= 4.735 ns)
    Info: + Longest register to register delay is 1.877 ns
        Info: 1: + IC(0.000 ns) + CELL(0.291 ns) = 0.291 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256|temp0[2]'
        Info: 2: + IC(0.321 ns) + CELL(1.265 ns) = 1.877 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256|temp0[2]'
        Info: Total cell delay = 1.556 ns ( 82.90 % )
        Info: Total interconnect delay = 0.321 ns ( 17.10 % )
    Info: - Smallest clock skew is -2.085 ns
        Info: + Shortest clock path from clock "sel_baud_rate[1]" to destination register is 16.170 ns
            Info: 1: + IC(0.000 ns) + CELL(1.845 ns) = 1.845 ns; Loc. = PIN_131; Fanout = 3; CLK Node = 'sel_baud_rate[1]'
            Info: 2: + IC(4.744 ns) + CELL(1.602 ns) = 8.191 ns; Loc. = LC9_4_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256|clock~33'
            Info: 3: + IC(0.321 ns) + CELL(1.436 ns) = 9.948 ns; Loc. = LC5_5_O1; Fanout = 4; COMB Node = 'divide_by_256:divide_256|clock~34'
            Info: 4: + IC(6.222 ns) + CELL(0.000 ns) = 16.170 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256|temp0[2]'
            Info: Total cell delay = 4.883 ns ( 30.20 % )
            Info: Total interconnect delay = 11.287 ns ( 69.80 % )
        Info: - Longest clock path from clock "sel_baud_rate[1]" to source register is 18.255 ns
            Info: 1: + IC(0.000 ns) + CELL(1.845 ns) = 1.845 ns; Loc. = PIN_131; Fanout = 3; CLK Node = 'sel_baud_rate[1]'
            Info: 2: + IC(4.742 ns) + CELL(1.602 ns) = 8.189 ns; Loc. = LC10_4_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256|clock~30'
            Info: 3: + IC(1.297 ns) + CELL(1.581 ns) = 11.067 ns; Loc. = LC3_5_O1; Fanout = 1; COMB Node = 'divide_by_256:divide_256|clock~31'
            Info: 4: + IC(0.321 ns) + CELL(0.645 ns) = 12.033 ns; Loc. = LC5_5_O1; Fanout = 4; COMB Node = 'divide_by_256:divide_256|clock~34'
            Info: 5: + IC(6.222 ns) + CELL(0.000 ns) = 18.255 ns; Loc. = LC5_15_Z2; Fanout = 2; REG Node = 'divide_by_256:divide_256|temp0[2]'
            Info: Total cell delay = 5.673 ns ( 31.08 % )
            Info: Total interconnect delay = 12.582 ns ( 68.92 % )