uart_clk.v

来自「Uart port 是一段不错的」· Verilog 代码 · 共 65 行

module uart_clk(sel_baud_rate,sys_clock,rest,clock,sample_clock);
input sys_clock,rest;
input[2:0] sel_baud_rate;
output clock,sample_clock;
//output sys_clock_by_13;
//output[7:0] temp;
//output[2:0] temp0;
wire clock,sample_clock;
reg[7:0] temp;
reg[2:0] temp0;

wire sys_clock_by_13;
 divide_by_13     divide_13(sys_clock_by_13,sys_clock,rest);
 divide_by_256    divide_256(clock,sample_clock,sel_baud_rate,sys_clock_by_13,rest);
endmodule
/////////////////////
module divide_by_13(sys_clock_by_13,sys_clock,rest);
input sys_clock,rest;
output sys_clock_by_13;
wire sys_clock_by_13;
reg [3:0] temp;
assign  sys_clock_by_13=temp[3];
always@(posedge sys_clock or posedge rest)
if(rest) temp<=4'b0000;
else if(temp==12) temp<=4'b0000;
  else temp<=temp+4'h1;
endmodule 
//////////////////////////
module divide_by_256(clock,sample_clk,sel_baud_rate,sys_clock_13,rest);
input rest,sys_clock_13;
input[2:0] sel_baud_rate;
output clock;
output sample_clk;
//output[7:0] temp;
//output[3:0] temp0;
reg clock;
reg[7:0] temp;
reg[3:0] temp0;
wire sample_clk;
assign sample_clk=temp0[2];
always@(posedge sys_clock_13 or posedge rest)
if(rest) temp<=0;
else if (temp==8'd255) temp<=0;
    else temp<=temp+8'h1;

always@(sel_baud_rate or  temp)
case (sel_baud_rate)
3'h0: clock<=temp[0];
3'h1: clock<=temp[1];
3'h2: clock<=temp[2];
3'h3: clock<=temp[3];
3'h4: clock<=temp[4];
3'h5: clock<=temp[5];
3'h6: clock<=temp[6];
3'h7: clock<=temp[7];
default :clock<=0;
endcase
   
always@( posedge clock or posedge rest)
if(rest) temp0<=0;
else if(temp0==7) temp0<=0;
 else temp0<=temp0+4'h1;
endmodule