usrt_receive.v

来自「Uart port 是一段不错的」· Verilog 代码 · 共 115 行

module usrt_receive(read_not_ready_out,clr_sample_counter,bit_counter,
                     sample_counter,rcv_shiftreg,inc_sample_counter,
                     clr_bit_counter,date_bus,
                     inc_bit_counter,shift,load,error1,error2,
                     //state,next_state,
                     serial,read_not_ready_in,
                     rest,clk);
input rest,clk;
input read_not_ready_in;
input serial;
//output[1:0] state,next_state;
output [word_size-1:0] rcv_shiftreg;
output [count_size:0] bit_counter,sample_counter;
output [word_size-1:0]  date_bus;
output read_not_ready_out,clr_sample_counter;
output inc_sample_counter,clr_bit_counter;
output inc_bit_counter,shift,load,error1,error2;
reg read_not_ready_out,clr_sample_counter;
reg inc_sample_counter,clr_bit_counter;
reg inc_bit_counter,shift,load,error1,error2;
reg [word_size-1:0] date_bus;
reg [word_size-1:0] rcv_shiftreg;
reg [count_size:0] bit_counter;
reg [count_size:0] sample_counter;
reg [1:0] state,next_state;
parameter count_size=3;
parameter word_size=8;
parameter idle=2'b00;
parameter starting=2'b01;
parameter receving=2'b10;
always@(posedge clk or posedge rest)
begin 
   if(rest) state<=idle;
   else state<=next_state;
end
 always@(state or serial or read_not_ready_in or sample_counter or bit_counter)
 begin
    read_not_ready_out=0;
    clr_sample_counter=0;
    clr_bit_counter=0;
    inc_sample_counter=0;
    inc_bit_counter=0;
    shift=0;
    load=0;
    error1=0;
    error2=0;
    next_state=state;
    case(state)
    idle: if(!serial) next_state=starting; 
             else next_state=idle;     
    starting:if(serial) 
                 begin 
                     clr_sample_counter=1;
                      next_state=idle;
                end
              else if(sample_counter!=3) inc_sample_counter=1;
                     else
                          begin 
                                 clr_sample_counter=1;
                                 next_state=receving;
                          end
    receving:if(sample_counter==word_size-1)
                   begin 
                        if(bit_counter==word_size) 
                               begin
                                 next_state=idle;
                                 clr_bit_counter=1;
                                 clr_sample_counter=1;
                                 read_not_ready_out=1;
                                 if(read_not_ready_in) error1=1;
                                    else if(serial) load=1;
                                          else error2=1;
                                end
                          else 
                               begin
                                  inc_bit_counter=1;
                                  shift=1;
                                  clr_sample_counter=1;
                                  next_state=receving;
                               end
                   end
              else inc_sample_counter=1;
   default: next_state=idle;
  endcase
end

always@(posedge clk or posedge rest)
if(rest) begin
              sample_counter<=0;
              rcv_shiftreg<=0;
              bit_counter<=0;
              date_bus<=0;
        end
else
       begin
            if(clr_sample_counter) 
                         sample_counter<=0;
                  else if(inc_sample_counter) 
                         sample_counter<=sample_counter+4'h1;
            if(clr_bit_counter)
                         bit_counter<=0;
                 else if(inc_bit_counter)
                         bit_counter<=bit_counter+4'h1;
               
           if(shift)
               begin
                //rcv_shiftreg[word_size]<=serial;
               rcv_shiftreg[word_size-1:0]<={serial,rcv_shiftreg[word_size-1:1]};
               end
                 else if(load) date_bus<=rcv_shiftreg[word_size-1:0];
       end
endmodule