uart_top.map.rpt

来自「Uart port 是一段不错的」· RPT 代码 · 共 320 行 · 第 1/2 页

;       |divide_by_256:divide_256|  ; 16 (16)     ; 11           ; 0           ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 11 (11)          ; 8 (8)           ; 0 (0)      ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256 ;
;    |uart_emitter:uart_emitter_a|  ; 28 (28)     ; 22           ; 0           ; 0    ; 0            ; 6 (6)        ; 18 (18)           ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |uart_top|uart_emitter:uart_emitter_a                      ;
;    |uart_receive:uart_receiver_a| ; 32 (32)     ; 26           ; 0           ; 0    ; 0            ; 6 (6)        ; 15 (15)           ; 11 (11)          ; 0 (0)           ; 0 (0)      ; |uart_top|uart_receive:uart_receiver_a                     ;
+-----------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |uart_top|uart_emitter:uart_emitter_a|state                                                                                                            ;
+------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+
; Name       ; state.over ; state.bit0 ; state.bit1 ; state.bit2 ; state.bit3 ; state.bit4 ; state.bit5 ; state.bit6 ; state.bit7 ; state.bit8 ; state.bit9 ; state.idle ;
+------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+
; state.idle ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ;
; state.bit9 ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 1          ; 1          ;
; state.bit8 ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 1          ; 0          ; 1          ;
; state.bit7 ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 1          ; 0          ; 0          ; 1          ;
; state.bit6 ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 1          ; 0          ; 0          ; 0          ; 1          ;
; state.bit5 ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 1          ; 0          ; 0          ; 0          ; 0          ; 1          ;
; state.bit4 ; 0          ; 0          ; 0          ; 0          ; 0          ; 1          ; 0          ; 0          ; 0          ; 0          ; 0          ; 1          ;
; state.bit3 ; 0          ; 0          ; 0          ; 0          ; 1          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 1          ;
; state.bit2 ; 0          ; 0          ; 0          ; 1          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 1          ;
; state.bit1 ; 0          ; 0          ; 1          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 1          ;
; state.bit0 ; 0          ; 1          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 1          ;
; state.over ; 1          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 0          ; 1          ;
+------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 63    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 39    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 26    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; uart_emitter:uart_emitter_a|serial     ; 11      ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+--------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_emitter:uart_emitter_a ;
+----------------+-------+-------------------------------------------------+
; Parameter Name ; Value ; Type                                            ;
+----------------+-------+-------------------------------------------------+
; idle           ; 0000  ; Binary                                          ;
; bit0           ; 0001  ; Binary                                          ;
; bit1           ; 0011  ; Binary                                          ;
; bit2           ; 0010  ; Binary                                          ;
; bit3           ; 0110  ; Binary                                          ;
; bit4           ; 0111  ; Binary                                          ;
; bit5           ; 0101  ; Binary                                          ;
; bit6           ; 0100  ; Binary                                          ;
; bit7           ; 1100  ; Binary                                          ;
; bit8           ; 1101  ; Binary                                          ;
; bit9           ; 1111  ; Binary                                          ;
; over           ; 1110  ; Binary                                          ;
+----------------+-------+-------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_receive:uart_receiver_a ;
+----------------+-------+--------------------------------------------------+
; Parameter Name ; Value ; Type                                             ;
+----------------+-------+--------------------------------------------------+
; state0         ; 0     ; Binary                                           ;
; state1         ; 1     ; Binary                                           ;
+----------------+-------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/verilog/uart/uart_top.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Mon Mar 12 00:16:09 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart_top -c uart_top
Info: Found 1 design units, including 1 entities, in source file uart_top.v
    Info: Found entity 1: uart_top
Info: Elaborating entity "uart_top" for the top level hierarchy
Warning: Using design file uart_clk.v, which is not specified as a design file for the current project, but contains definitions for 3 design units and 3 entities in project
    Info: Found entity 1: uart_clk
    Info: Found entity 2: divide_by_13
    Info: Found entity 3: divide_by_256
Info: Elaborating entity "uart_clk" for hierarchy "uart_clk:uart_clk_gen_a"
Info (10035): Verilog HDL or VHDL information at uart_clk.v(9): object "temp" declared but not used
Info (10035): Verilog HDL or VHDL information at uart_clk.v(10): object "temp0" declared but not used
Info: Elaborating entity "divide_by_13" for hierarchy "uart_clk:uart_clk_gen_a|divide_by_13:divide_13"
Info: Elaborating entity "divide_by_256" for hierarchy "uart_clk:uart_clk_gen_a|divide_by_256:divide_256"
Warning: Using design file uart_emitter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: uart_emitter
Info: Elaborating entity "uart_emitter" for hierarchy "uart_emitter:uart_emitter_a"
Warning: Using design file uart_receive.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: uart_receive
Info: Elaborating entity "uart_receive" for hierarchy "uart_receive:uart_receiver_a"
Info: Power-up level of register "uart_receive:uart_receiver_a|error" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "uart_receive:uart_receiver_a|error" with stuck data_in port to stuck value VCC
Info: State machine "|uart_top|uart_emitter:uart_emitter_a|state" contains 12 states
Info: Selected Auto state machine encoding method for state machine "|uart_top|uart_emitter:uart_emitter_a|state"
Info: Encoding result for state machine "|uart_top|uart_emitter:uart_emitter_a|state"
    Info: Completed encoding using 12 state bits
        Info: Encoded state bit "uart_emitter:uart_emitter_a|state.over"
        Info: Encoded state bit "uart_emitter:uart_emitter_a|state.bit0"
        Info: Encoded state bit "uart_emitter:uart_emitter_a|state.bit1"
        Info: Encoded state bit "uart_emitter:uart_emitter_a|state.bit2"
        Info: Encoded state bit "uart_emitter:uart_emitter_a|state.bit3"
        Info: Encoded state bit "uart_emitter:uart_emitter_a|state.bit4"
        Info: Encoded state bit "uart_emitter:uart_emitter_a|state.bit5"
        Info: Encoded state bit "uart_emitter:uart_emitter_a|state.bit6"
        Info: Encoded state bit "uart_emitter:uart_emitter_a|state.bit7"
        Info: Encoded state bit "uart_emitter:uart_emitter_a|state.bit8"
        Info: Encoded state bit "uart_emitter:uart_emitter_a|state.bit9"
        Info: Encoded state bit "uart_emitter:uart_emitter_a|state.idle"
    Info: State "|uart_top|uart_emitter:uart_emitter_a|state.idle" uses code string "000000000000"
    Info: State "|uart_top|uart_emitter:uart_emitter_a|state.bit9" uses code string "000000000011"
    Info: State "|uart_top|uart_emitter:uart_emitter_a|state.bit8" uses code string "000000000101"
    Info: State "|uart_top|uart_emitter:uart_emitter_a|state.bit7" uses code string "000000001001"
    Info: State "|uart_top|uart_emitter:uart_emitter_a|state.bit6" uses code string "000000010001"
    Info: State "|uart_top|uart_emitter:uart_emitter_a|state.bit5" uses code string "000000100001"
    Info: State "|uart_top|uart_emitter:uart_emitter_a|state.bit4" uses code string "000001000001"
    Info: State "|uart_top|uart_emitter:uart_emitter_a|state.bit3" uses code string "000010000001"
    Info: State "|uart_top|uart_emitter:uart_emitter_a|state.bit2" uses code string "000100000001"
    Info: State "|uart_top|uart_emitter:uart_emitter_a|state.bit1" uses code string "001000000001"
    Info: State "|uart_top|uart_emitter:uart_emitter_a|state.bit0" uses code string "010000000001"
    Info: State "|uart_top|uart_emitter:uart_emitter_a|state.over" uses code string "100000000001"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "error" stuck at VCC
Info: Implemented 121 device resources after synthesis - the final resource count might be different
    Info: Implemented 14 input pins
    Info: Implemented 22 output pins
    Info: Implemented 85 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Processing ended: Mon Mar 12 00:16:18 2007
    Info: Elapsed time: 00:00:11