uart_emitter.map.eqn

Uart port 是一段不错的

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--A1L32Q is serial~reg0
--operation mode is normal

A1L32Q_lut_out = !A1L1 & !A1L2 & !A1L3 & A1L5;
A1L32Q = DFFE(A1L32Q_lut_out, clock, !rest, , );


--A1L28Q is finish_F~reg0
--operation mode is normal

A1L28Q_lut_out = state.over # A1L28Q & state.idle;
A1L28Q = DFFE(A1L28Q_lut_out, clock, !rest, , );


--bus_reg[0] is bus_reg[0]
--operation mode is normal

bus_reg[0]_lut_out = bus[0];
bus_reg[0] = DFFE(bus_reg[0]_lut_out, clock, , , A1L25);


--bus_reg[2] is bus_reg[2]
--operation mode is normal

bus_reg[2]_lut_out = bus[2];
bus_reg[2] = DFFE(bus_reg[2]_lut_out, clock, , , A1L25);


--state.bit3 is state.bit3
--operation mode is normal

state.bit3_lut_out = state.bit2;
state.bit3 = DFFE(state.bit3_lut_out, clock, !rest, , );


--state.bit1 is state.bit1
--operation mode is normal

state.bit1_lut_out = state.bit0;
state.bit1 = DFFE(state.bit1_lut_out, clock, !rest, , );


--A1L1 is Select~134
--operation mode is normal

A1L1 = bus_reg[0] & (state.bit1 # bus_reg[2] & state.bit3) # !bus_reg[0] & bus_reg[2] & state.bit3;


--bus_reg[4] is bus_reg[4]
--operation mode is normal

bus_reg[4]_lut_out = bus[4];
bus_reg[4] = DFFE(bus_reg[4]_lut_out, clock, , , A1L25);


--bus_reg[7] is bus_reg[7]
--operation mode is normal

bus_reg[7]_lut_out = bus[7];
bus_reg[7] = DFFE(bus_reg[7]_lut_out, clock, , , A1L25);


--state.bit8 is state.bit8
--operation mode is normal

state.bit8_lut_out = state.bit7;
state.bit8 = DFFE(state.bit8_lut_out, clock, !rest, , );


--state.bit5 is state.bit5
--operation mode is normal

state.bit5_lut_out = state.bit4;
state.bit5 = DFFE(state.bit5_lut_out, clock, !rest, , );


--A1L2 is Select~135
--operation mode is normal

A1L2 = bus_reg[4] & (state.bit5 # bus_reg[7] & state.bit8) # !bus_reg[4] & bus_reg[7] & state.bit8;


--state.bit9 is state.bit9
--operation mode is normal

state.bit9_lut_out = state.bit8;
state.bit9 = DFFE(state.bit9_lut_out, clock, !rest, , );


--state.over is state.over
--operation mode is normal

state.over_lut_out = state.bit9;
state.over = DFFE(state.over_lut_out, clock, !rest, , );


--state.idle is state.idle
--operation mode is normal

state.idle_lut_out = !state.over & (state.idle # load_bus_reg);
state.idle = DFFE(state.idle_lut_out, clock, !rest, , );


--A1L3 is Select~136
--operation mode is normal

A1L3 = state.bit9 # !A1L32Q & (state.over # !state.idle);


--A1L25 is bus_reg[7]~0
--operation mode is normal

A1L25 = load_bus_reg & (!rest & !state.idle);


--state.bit2 is state.bit2
--operation mode is normal

state.bit2_lut_out = state.bit1;
state.bit2 = DFFE(state.bit2_lut_out, clock, !rest, , );


--state.bit0 is state.bit0
--operation mode is normal

state.bit0_lut_out = load_bus_reg & (!state.idle);
state.bit0 = DFFE(state.bit0_lut_out, clock, !rest, , );


--state.bit7 is state.bit7
--operation mode is normal

state.bit7_lut_out = state.bit6;
state.bit7 = DFFE(state.bit7_lut_out, clock, !rest, , );


--state.bit4 is state.bit4
--operation mode is normal

state.bit4_lut_out = state.bit3;
state.bit4 = DFFE(state.bit4_lut_out, clock, !rest, , );


--state.bit6 is state.bit6
--operation mode is normal

state.bit6_lut_out = state.bit5;
state.bit6 = DFFE(state.bit6_lut_out, clock, !rest, , );


--bus_reg[6] is bus_reg[6]
--operation mode is normal

bus_reg[6]_lut_out = bus[6];
bus_reg[6] = DFFE(bus_reg[6]_lut_out, clock, , , A1L25);


--bus_reg[3] is bus_reg[3]
--operation mode is normal

bus_reg[3]_lut_out = bus[3];
bus_reg[3] = DFFE(bus_reg[3]_lut_out, clock, , , A1L25);


--A1L4 is Select~144
--operation mode is normal

A1L4 = bus_reg[6] & !state.bit7 & (!state.bit4 # !bus_reg[3]) # !bus_reg[6] & (!state.bit4 # !bus_reg[3]);

--A1L6 is Select~148
--operation mode is normal

A1L6 = bus_reg[6] & !state.bit7 & (!state.bit4 # !bus_reg[3]) # !bus_reg[6] & (!state.bit4 # !bus_reg[3]);


--bus_reg[5] is bus_reg[5]
--operation mode is normal

bus_reg[5]_lut_out = bus[5];
bus_reg[5] = DFFE(bus_reg[5]_lut_out, clock, , , A1L25);


--bus_reg[1] is bus_reg[1]
--operation mode is normal

bus_reg[1]_lut_out = bus[1];
bus_reg[1] = DFFE(bus_reg[1]_lut_out, clock, , , A1L25);


--A1L5 is Select~146
--operation mode is normal

A1L5 = (bus_reg[5] & !state.bit6 & (!state.bit2 # !bus_reg[1]) # !bus_reg[5] & (!state.bit2 # !bus_reg[1])) & CASCADE(A1L6);


--clock is clock
--operation mode is input

clock = INPUT();


--rest is rest
--operation mode is input

rest = INPUT();


--bus[0] is bus[0]
--operation mode is input

bus[0] = INPUT();


--load_bus_reg is load_bus_reg
--operation mode is input

load_bus_reg = INPUT();


--bus[2] is bus[2]
--operation mode is input

bus[2] = INPUT();


--bus[4] is bus[4]
--operation mode is input

bus[4] = INPUT();


--bus[7] is bus[7]
--operation mode is input

bus[7] = INPUT();


--bus[6] is bus[6]
--operation mode is input

bus[6] = INPUT();


--bus[3] is bus[3]
--operation mode is input

bus[3] = INPUT();


--bus[5] is bus[5]
--operation mode is input

bus[5] = INPUT();


--bus[1] is bus[1]
--operation mode is input

bus[1] = INPUT();


--serial is serial
--operation mode is output

serial = OUTPUT(!A1L32Q);


--finish_F is finish_F
--operation mode is output

finish_F = OUTPUT(A1L28Q);