uart_clk.fit.summary

来自「Uart port 是一段不错的」· SUMMARY 代码 · 共 13 行

Fitter Status : Successful - Mon Dec 11 19:42:07 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : uart_clk
Top-level Entity Name : uart_clk
Family : APEX20KE
Device : EP20K200EQC240-3
Timing Models : Final
Total logic elements : 20 / 8,320 ( < 1 % )
Total pins : 7 / 168 ( 4 % )
Total virtual pins : 0
Total memory bits : 0 / 106,496 ( 0 % )
Total PLLs : 0