uart_clk.fit.eqn

来自「Uart port 是一段不错的」· EQN 代码 · 共 226 行

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--C1_temp[5] is divide_by_256:divide_256|temp[5] at LC6_4_O1
--operation mode is arithmetic

C1_temp[5]_lut_out = C1_temp[5] $ C1L20;
C1_temp[5] = DFFE(C1_temp[5]_lut_out, GLOBAL(B1_temp[3]), !GLOBAL(rest), , );

--C1L22 is divide_by_256:divide_256|temp[5]~57 at LC6_4_O1
--operation mode is arithmetic

C1L22 = CARRY(!C1L20 # !C1_temp[5]);


--C1_temp[6] is divide_by_256:divide_256|temp[6] at LC7_4_O1
--operation mode is arithmetic

C1_temp[6]_lut_out = C1_temp[6] $ !C1L22;
C1_temp[6] = DFFE(C1_temp[6]_lut_out, GLOBAL(B1_temp[3]), !GLOBAL(rest), , );

--C1L24 is divide_by_256:divide_256|temp[6]~60 at LC7_4_O1
--operation mode is arithmetic

C1L24 = CARRY(C1_temp[6] & !C1L22);


--C1_temp[4] is divide_by_256:divide_256|temp[4] at LC5_4_O1
--operation mode is arithmetic

C1_temp[4]_lut_out = C1_temp[4] $ !C1L18;
C1_temp[4] = DFFE(C1_temp[4]_lut_out, GLOBAL(B1_temp[3]), !GLOBAL(rest), , );

--C1L20 is divide_by_256:divide_256|temp[4]~63 at LC5_4_O1
--operation mode is arithmetic

C1L20 = CARRY(C1_temp[4] & !C1L18);


--C1L1 is divide_by_256:divide_256|clock~30 at LC10_4_O1
--operation mode is normal

C1L1 = sel_baud_rate[1] & (C1_temp[6] # sel_baud_rate[0]) # !sel_baud_rate[1] & (!sel_baud_rate[0] & C1_temp[4]);


--C1_temp[7] is divide_by_256:divide_256|temp[7] at LC8_4_O1
--operation mode is normal

C1_temp[7]_lut_out = C1L24 $ C1_temp[7];
C1_temp[7] = DFFE(C1_temp[7]_lut_out, GLOBAL(B1_temp[3]), !GLOBAL(rest), , );


--C1L2 is divide_by_256:divide_256|clock~31 at LC3_5_O1
--operation mode is normal

C1L2 = C1L1 & (C1_temp[7] # !sel_baud_rate[0]) # !C1L1 & (C1_temp[5] & sel_baud_rate[0]);


--C1_temp[2] is divide_by_256:divide_256|temp[2] at LC3_4_O1
--operation mode is arithmetic

C1_temp[2]_lut_out = C1_temp[2] $ !C1L14;
C1_temp[2] = DFFE(C1_temp[2]_lut_out, GLOBAL(B1_temp[3]), !GLOBAL(rest), , );

--C1L16 is divide_by_256:divide_256|temp[2]~69 at LC3_4_O1
--operation mode is arithmetic

C1L16 = CARRY(C1_temp[2] & !C1L14);


--C1_temp[1] is divide_by_256:divide_256|temp[1] at LC2_4_O1
--operation mode is arithmetic

C1_temp[1]_lut_out = C1_temp[1] $ C1L12;
C1_temp[1] = DFFE(C1_temp[1]_lut_out, GLOBAL(B1_temp[3]), !GLOBAL(rest), , );

--C1L14 is divide_by_256:divide_256|temp[1]~72 at LC2_4_O1
--operation mode is arithmetic

C1L14 = CARRY(!C1L12 # !C1_temp[1]);


--C1_temp[0] is divide_by_256:divide_256|temp[0] at LC1_4_O1
--operation mode is arithmetic

C1_temp[0]_lut_out = !C1_temp[0];
C1_temp[0] = DFFE(C1_temp[0]_lut_out, GLOBAL(B1_temp[3]), !GLOBAL(rest), , );

--C1L12 is divide_by_256:divide_256|temp[0]~75 at LC1_4_O1
--operation mode is arithmetic

C1L12 = CARRY(C1_temp[0]);


--C1L3 is divide_by_256:divide_256|clock~32 at LC3_3_O1
--operation mode is normal

C1L3 = sel_baud_rate[0] & (C1_temp[1] # sel_baud_rate[1]) # !sel_baud_rate[0] & (!sel_baud_rate[1] & C1_temp[0]);


--C1_temp[3] is divide_by_256:divide_256|temp[3] at LC4_4_O1
--operation mode is arithmetic

C1_temp[3]_lut_out = C1_temp[3] $ C1L16;
C1_temp[3] = DFFE(C1_temp[3]_lut_out, GLOBAL(B1_temp[3]), !GLOBAL(rest), , );

--C1L18 is divide_by_256:divide_256|temp[3]~78 at LC4_4_O1
--operation mode is arithmetic

C1L18 = CARRY(!C1L16 # !C1_temp[3]);


--C1L4 is divide_by_256:divide_256|clock~33 at LC9_4_O1
--operation mode is normal

C1L4 = sel_baud_rate[1] & (C1L3 & C1_temp[3] # !C1L3 & (C1_temp[2])) # !sel_baud_rate[1] & (C1L3);


--C1L5 is divide_by_256:divide_256|clock~34 at LC5_5_O1
--operation mode is normal

C1L5 = sel_baud_rate[2] & (C1L2) # !sel_baud_rate[2] & C1L4;


--C1_temp0[2] is divide_by_256:divide_256|temp0[2] at LC5_15_Z2
--operation mode is normal

C1_temp0[2]_lut_out = C1_temp0[2] $ (C1_temp0[1] & C1_temp0[0]);
C1_temp0[2] = DFFE(C1_temp0[2]_lut_out, GLOBAL(C1L5), !GLOBAL(rest), , );


--B1_temp[3] is divide_by_13:divide_13|temp[3] at LC5_16_N1
--operation mode is normal

B1_temp[3]_lut_out = B1_temp[1] & (B1_temp[3] $ (B1_temp[0] & B1_temp[2])) # !B1_temp[1] & B1_temp[3] & (B1_temp[0] # !B1_temp[2]);
B1_temp[3] = DFFE(B1_temp[3]_lut_out, GLOBAL(sys_clock), !GLOBAL(rest), , );


--C1_temp0[1] is divide_by_256:divide_256|temp0[1] at LC6_15_Z2
--operation mode is normal

C1_temp0[1]_lut_out = C1_temp0[1] $ C1_temp0[0];
C1_temp0[1] = DFFE(C1_temp0[1]_lut_out, GLOBAL(C1L5), !GLOBAL(rest), , );


--C1_temp0[0] is divide_by_256:divide_256|temp0[0] at LC3_15_Z2
--operation mode is normal

C1_temp0[0]_lut_out = !C1_temp0[0];
C1_temp0[0] = DFFE(C1_temp0[0]_lut_out, GLOBAL(C1L5), !GLOBAL(rest), , );


--B1_temp[1] is divide_by_13:divide_13|temp[1] at LC7_16_N1
--operation mode is normal

B1_temp[1]_lut_out = B1_temp[1] $ (B1_temp[0]);
B1_temp[1] = DFFE(B1_temp[1]_lut_out, GLOBAL(sys_clock), !GLOBAL(rest), , );


--B1_temp[0] is divide_by_13:divide_13|temp[0] at LC6_16_N1
--operation mode is normal

B1_temp[0]_lut_out = !B1_temp[0] & (B1_temp[1] # !B1_temp[2] # !B1_temp[3]);
B1_temp[0] = DFFE(B1_temp[0]_lut_out, GLOBAL(sys_clock), !GLOBAL(rest), , );


--B1_temp[2] is divide_by_13:divide_13|temp[2] at LC3_16_N1
--operation mode is normal

B1_temp[2]_lut_out = B1_temp[1] & (B1_temp[0] $ B1_temp[2]) # !B1_temp[1] & B1_temp[2] & (B1_temp[0] # !B1_temp[3]);
B1_temp[2] = DFFE(B1_temp[2]_lut_out, GLOBAL(sys_clock), !GLOBAL(rest), , );


--sel_baud_rate[0] is sel_baud_rate[0] at PIN_138
--operation mode is input

sel_baud_rate[0] = INPUT();


--sel_baud_rate[1] is sel_baud_rate[1] at PIN_131
--operation mode is input

sel_baud_rate[1] = INPUT();


--sel_baud_rate[2] is sel_baud_rate[2] at PIN_37
--operation mode is input

sel_baud_rate[2] = INPUT();


--rest is rest at PIN_88
--operation mode is input

rest = INPUT();


--sys_clock is sys_clock at PIN_154
--operation mode is input

sys_clock = INPUT();


--clock is clock at PIN_36
--operation mode is output

clock = OUTPUT(C1L5);


--sample_clock is sample_clock at PIN_82
--operation mode is output

sample_clock = OUTPUT(C1_temp0[2]);