uart_receive.map.eqn

来自「Uart port 是一段不错的」· EQN 代码 · 共 388 行

-- Copyright (C) 1991-2005 Altera Corporation
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-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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--A1L16Q is bus[0]~reg0
--operation mode is normal

A1L16Q_lut_out = bus_reg[0];
A1L16Q = DFFE(A1L16Q_lut_out, clk, , , A1L15);


--A1L18Q is bus[1]~reg0
--operation mode is normal

A1L18Q_lut_out = bus_reg[1];
A1L18Q = DFFE(A1L18Q_lut_out, clk, , , A1L15);


--A1L20Q is bus[2]~reg0
--operation mode is normal

A1L20Q_lut_out = bus_reg[2];
A1L20Q = DFFE(A1L20Q_lut_out, clk, , , A1L15);


--A1L22Q is bus[3]~reg0
--operation mode is normal

A1L22Q_lut_out = bus_reg[3];
A1L22Q = DFFE(A1L22Q_lut_out, clk, , , A1L15);


--A1L24Q is bus[4]~reg0
--operation mode is normal

A1L24Q_lut_out = bus_reg[4];
A1L24Q = DFFE(A1L24Q_lut_out, clk, , , A1L15);


--A1L26Q is bus[5]~reg0
--operation mode is normal

A1L26Q_lut_out = bus_reg[5];
A1L26Q = DFFE(A1L26Q_lut_out, clk, , , A1L15);


--A1L28Q is bus[6]~reg0
--operation mode is normal

A1L28Q_lut_out = bus_reg[6];
A1L28Q = DFFE(A1L28Q_lut_out, clk, , , A1L15);


--A1L30Q is bus[7]~reg0
--operation mode is normal

A1L30Q_lut_out = bus_reg[7];
A1L30Q = DFFE(A1L30Q_lut_out, clk, , , A1L15);


--A1L6Q is bit_counter[0]~reg0
--operation mode is normal

A1L6Q_lut_out = !A1L6Q & (A1L8Q # A1L10Q # !A1L12Q);
A1L6Q = DFFE(A1L6Q_lut_out, clk, !rest, , A1L5);


--A1L8Q is bit_counter[1]~reg0
--operation mode is normal

A1L8Q_lut_out = A1L8Q $ (!A1L56 & A1L6Q & state);
A1L8Q = DFFE(A1L8Q_lut_out, clk, !rest, , );


--A1L10Q is bit_counter[2]~reg0
--operation mode is normal

A1L10Q_lut_out = A1L10Q $ (A1L8Q & A1L6Q & A1L5);
A1L10Q = DFFE(A1L10Q_lut_out, clk, !rest, , );


--A1L12Q is bit_counter[3]~reg0
--operation mode is normal

A1L12Q_lut_out = A1L6Q & (A1L12Q $ (A1L8Q & A1L10Q)) # !A1L6Q & A1L12Q & (A1L8Q # A1L10Q);
A1L12Q = DFFE(A1L12Q_lut_out, clk, !rest, , A1L5);


--A1L44Q is counter[0]~reg0
--operation mode is normal

A1L44Q_lut_out = A1L44Q $ A1L59;
A1L44Q = DFFE(A1L44Q_lut_out, clk, !rest, , );


--A1L46Q is counter[1]~reg0
--operation mode is normal

A1L46Q_lut_out = A1L59 & !A1L5 & (A1L46Q $ A1L44Q) # !A1L59 & A1L46Q;
A1L46Q = DFFE(A1L46Q_lut_out, clk, !rest, , );


--A1L49Q is counter[2]~reg0
--operation mode is normal

A1L49Q_lut_out = A1L59 & A1L48 & (A1L49Q $ A1L1) # !A1L59 & (A1L49Q);
A1L49Q = DFFE(A1L49Q_lut_out, clk, !rest, , );


--A1L51Q is counter[3]~reg0
--operation mode is normal

A1L51Q_lut_out = A1L59 & !A1L5 & (A1L51Q $ A1L2) # !A1L59 & A1L51Q;
A1L51Q = DFFE(A1L51Q_lut_out, clk, !rest, , );


--A1L54Q is finish_s~reg0
--operation mode is normal

A1L54Q_lut_out = A1L54Q # A1L5 & A1L58 & serial;
A1L54Q = DFFE(A1L54Q_lut_out, clk, !rest, , );


--bus_reg[0] is bus_reg[0]
--operation mode is normal

bus_reg[0]_lut_out = bus_reg[1];
bus_reg[0] = DFFE(bus_reg[0]_lut_out, clk, , , A1L33);


--state is state
--operation mode is normal

state_lut_out = A1L60 # A1L57 & !state & !serial;
state = DFFE(state_lut_out, clk, !rest, , );


--A1L56 is rtl~1
--operation mode is normal

A1L56 = A1L51Q # !A1L46Q # !A1L44Q # !A1L49Q;


--A1L5 is bit_counter[0]~162
--operation mode is normal

A1L5 = state & (!A1L56);


--A1L58 is rtl~233
--operation mode is normal

A1L58 = A1L12Q & !A1L6Q & !A1L8Q & !A1L10Q;


--A1L15 is bus[0]~15
--operation mode is normal

A1L15 = A1L5 & A1L58 & serial & !rest;


--bus_reg[1] is bus_reg[1]
--operation mode is normal

bus_reg[1]_lut_out = bus_reg[2];
bus_reg[1] = DFFE(bus_reg[1]_lut_out, clk, , , A1L33);


--bus_reg[2] is bus_reg[2]
--operation mode is normal

bus_reg[2]_lut_out = bus_reg[3];
bus_reg[2] = DFFE(bus_reg[2]_lut_out, clk, , , A1L33);


--bus_reg[3] is bus_reg[3]
--operation mode is normal

bus_reg[3]_lut_out = bus_reg[4];
bus_reg[3] = DFFE(bus_reg[3]_lut_out, clk, , , A1L33);


--bus_reg[4] is bus_reg[4]
--operation mode is normal

bus_reg[4]_lut_out = bus_reg[5];
bus_reg[4] = DFFE(bus_reg[4]_lut_out, clk, , , A1L33);


--bus_reg[5] is bus_reg[5]
--operation mode is normal

bus_reg[5]_lut_out = bus_reg[6];
bus_reg[5] = DFFE(bus_reg[5]_lut_out, clk, , , A1L33);


--bus_reg[6] is bus_reg[6]
--operation mode is normal

bus_reg[6]_lut_out = bus_reg[7];
bus_reg[6] = DFFE(bus_reg[6]_lut_out, clk, , , A1L33);


--bus_reg[7] is bus_reg[7]
--operation mode is normal

bus_reg[7]_lut_out = serial;
bus_reg[7] = DFFE(bus_reg[7]_lut_out, clk, , , A1L33);


--A1L59 is rtl~234
--operation mode is normal

A1L59 = state & (A1L56 # !A1L58) # !state & (!serial);


--A1L57 is rtl~8
--operation mode is normal

A1L57 = A1L44Q & A1L46Q & !A1L49Q & !A1L51Q;


--A1L48 is counter[2]~608
--operation mode is normal

A1L48 = state & A1L56 # !state & (!A1L57);


--A1L1 is add~202
--operation mode is normal

A1L1 = A1L44Q & A1L46Q;


--A1L2 is add~203
--operation mode is normal

A1L2 = A1L49Q & A1L44Q & A1L46Q;


--A1L33 is bus_reg[0]~71
--operation mode is normal

A1L33 = state & !rest & !A1L58 & !A1L56;


--A1L60 is rtl~235
--operation mode is normal

A1L60 = state & (A1L56 # !A1L58);


--clk is clk
--operation mode is input

clk = INPUT();


--serial is serial
--operation mode is input

serial = INPUT();


--rest is rest
--operation mode is input

rest = INPUT();


--bus[0] is bus[0]
--operation mode is output

bus[0] = OUTPUT(A1L16Q);


--bus[1] is bus[1]
--operation mode is output

bus[1] = OUTPUT(A1L18Q);


--bus[2] is bus[2]
--operation mode is output

bus[2] = OUTPUT(A1L20Q);


--bus[3] is bus[3]
--operation mode is output

bus[3] = OUTPUT(A1L22Q);


--bus[4] is bus[4]
--operation mode is output

bus[4] = OUTPUT(A1L24Q);


--bus[5] is bus[5]
--operation mode is output

bus[5] = OUTPUT(A1L26Q);


--bus[6] is bus[6]
--operation mode is output

bus[6] = OUTPUT(A1L28Q);


--bus[7] is bus[7]
--operation mode is output

bus[7] = OUTPUT(A1L30Q);


--bit_counter[0] is bit_counter[0]
--operation mode is output

bit_counter[0] = OUTPUT(A1L6Q);


--bit_counter[1] is bit_counter[1]
--operation mode is output

bit_counter[1] = OUTPUT(A1L8Q);


--bit_counter[2] is bit_counter[2]
--operation mode is output

bit_counter[2] = OUTPUT(A1L10Q);


--bit_counter[3] is bit_counter[3]
--operation mode is output

bit_counter[3] = OUTPUT(A1L12Q);


--error is error
--operation mode is output

error = OUTPUT(VCC);


--counter[0] is counter[0]
--operation mode is output

counter[0] = OUTPUT(A1L44Q);


--counter[1] is counter[1]
--operation mode is output

counter[1] = OUTPUT(A1L46Q);


--counter[2] is counter[2]
--operation mode is output

counter[2] = OUTPUT(A1L49Q);


--counter[3] is counter[3]
--operation mode is output

counter[3] = OUTPUT(A1L51Q);


--finish_s is finish_s
--operation mode is output

finish_s = OUTPUT(A1L54Q);