uart_top.map.eqn

来自「Uart port 是一段不错的」· EQN 代码 · 共 848 行 · 第 1/2 页

C1_bus_reg[7]_lut_out = date_bus[7];
C1_bus_reg[7] = DFFE(C1_bus_reg[7]_lut_out, F1_temp0[2], , , C1L16);


--C1_state.bit8 is uart_emitter:uart_emitter_a|state.bit8
--operation mode is normal

C1_state.bit8_lut_out = C1_state.bit7;
C1_state.bit8 = DFFE(C1_state.bit8_lut_out, F1_temp0[2], !rest, , );


--C1_state.bit5 is uart_emitter:uart_emitter_a|state.bit5
--operation mode is normal

C1_state.bit5_lut_out = C1_state.bit4;
C1_state.bit5 = DFFE(C1_state.bit5_lut_out, F1_temp0[2], !rest, , );


--C1L2 is uart_emitter:uart_emitter_a|Select~136
--operation mode is normal

C1L2 = C1_bus_reg[4] & (C1_state.bit5 # C1_bus_reg[7] & C1_state.bit8) # !C1_bus_reg[4] & C1_bus_reg[7] & C1_state.bit8;


--C1_state.bit9 is uart_emitter:uart_emitter_a|state.bit9
--operation mode is normal

C1_state.bit9_lut_out = C1_state.bit8;
C1_state.bit9 = DFFE(C1_state.bit9_lut_out, F1_temp0[2], !rest, , );


--C1L3 is uart_emitter:uart_emitter_a|Select~137
--operation mode is normal

C1L3 = C1_state.bit9 # !C1_serial & (C1_state.over # !C1_state.idle);


--E1_temp[3] is uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[3]
--operation mode is normal

E1_temp[3]_lut_out = E1_temp[3] & (E1_temp[1] $ E1_temp[0] # !E1_temp[2]) # !E1_temp[3] & E1_temp[1] & E1_temp[0] & E1_temp[2];
E1_temp[3] = DFFE(E1_temp[3]_lut_out, sys_clock, !rest, , );


--F1_temp0[1] is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[1]
--operation mode is normal

F1_temp0[1]_lut_out = F1_temp0[1] $ F1_temp0[0];
F1_temp0[1] = DFFE(F1_temp0[1]_lut_out, F1L5, !rest, , );


--F1_temp0[0] is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[0]
--operation mode is normal

F1_temp0[0]_lut_out = !F1_temp0[0];
F1_temp0[0] = DFFE(F1_temp0[0]_lut_out, F1L5, !rest, , );


--D1L37 is uart_receive:uart_receiver_a|state~155
--operation mode is normal

D1L37 = !A1L35 # !A1L37;


--A1L38 is rtl~111
--operation mode is normal

A1L38 = D1_counter[0] & D1_counter[1] & !D1_counter[2] & !D1_counter[3];


--D1L19 is uart_receive:uart_receiver_a|bus_reg[0]~71
--operation mode is normal

D1L19 = D1_state & A1L35 & !rest & !A1L37;


--C1L16 is uart_emitter:uart_emitter_a|bus_reg[7]~0
--operation mode is normal

C1L16 = load_bus_reg & (!rest & !C1_state.idle);


--C1_state.bit2 is uart_emitter:uart_emitter_a|state.bit2
--operation mode is normal

C1_state.bit2_lut_out = C1_state.bit1;
C1_state.bit2 = DFFE(C1_state.bit2_lut_out, F1_temp0[2], !rest, , );


--C1_state.bit0 is uart_emitter:uart_emitter_a|state.bit0
--operation mode is normal

C1_state.bit0_lut_out = load_bus_reg & (!C1_state.idle);
C1_state.bit0 = DFFE(C1_state.bit0_lut_out, F1_temp0[2], !rest, , );


--C1_state.bit7 is uart_emitter:uart_emitter_a|state.bit7
--operation mode is normal

C1_state.bit7_lut_out = C1_state.bit6;
C1_state.bit7 = DFFE(C1_state.bit7_lut_out, F1_temp0[2], !rest, , );


--C1_state.bit4 is uart_emitter:uart_emitter_a|state.bit4
--operation mode is normal

C1_state.bit4_lut_out = C1_state.bit3;
C1_state.bit4 = DFFE(C1_state.bit4_lut_out, F1_temp0[2], !rest, , );


--E1_temp[1] is uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[1]
--operation mode is normal

E1_temp[1]_lut_out = E1_temp[1] $ E1_temp[0];
E1_temp[1] = DFFE(E1_temp[1]_lut_out, sys_clock, !rest, , );


--E1_temp[0] is uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[0]
--operation mode is normal

E1_temp[0]_lut_out = !E1_temp[0] & (E1_temp[1] # !E1_temp[2] # !E1_temp[3]);
E1_temp[0] = DFFE(E1_temp[0]_lut_out, sys_clock, !rest, , );


--E1_temp[2] is uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[2]
--operation mode is normal

E1_temp[2]_lut_out = E1_temp[1] & (E1_temp[2] $ E1_temp[0]) # !E1_temp[1] & E1_temp[2] & (E1_temp[0] # !E1_temp[3]);
E1_temp[2] = DFFE(E1_temp[2]_lut_out, sys_clock, !rest, , );


--A1L39 is rtl~112
--operation mode is normal

A1L39 = D1_counter[0] & D1_counter[1];


--D1L32 is uart_receive:uart_receiver_a|counter~633
--operation mode is normal

D1L32 = D1_state & (A1L39 $ !D1_counter[2]) # !D1_state & (C1_serial # !D1_counter[2]);

--D1L34 is uart_receive:uart_receiver_a|counter~638
--operation mode is normal

D1L34 = D1_state & (A1L39 $ !D1_counter[2]) # !D1_state & (C1_serial # !D1_counter[2]);


--D1L33 is uart_receive:uart_receiver_a|counter~636
--operation mode is normal

D1L33 = (A1L38 # D1_counter[2] $ !A1L39 # !C1_serial) & CASCADE(D1L34);


--C1_state.bit6 is uart_emitter:uart_emitter_a|state.bit6
--operation mode is normal

C1_state.bit6_lut_out = C1_state.bit5;
C1_state.bit6 = DFFE(C1_state.bit6_lut_out, F1_temp0[2], !rest, , );


--C1_bus_reg[6] is uart_emitter:uart_emitter_a|bus_reg[6]
--operation mode is normal

C1_bus_reg[6]_lut_out = date_bus[6];
C1_bus_reg[6] = DFFE(C1_bus_reg[6]_lut_out, F1_temp0[2], , , C1L16);


--C1_bus_reg[3] is uart_emitter:uart_emitter_a|bus_reg[3]
--operation mode is normal

C1_bus_reg[3]_lut_out = date_bus[3];
C1_bus_reg[3] = DFFE(C1_bus_reg[3]_lut_out, F1_temp0[2], , , C1L16);


--C1L4 is uart_emitter:uart_emitter_a|Select~144
--operation mode is normal

C1L4 = C1_bus_reg[6] & !C1_state.bit7 & (!C1_state.bit4 # !C1_bus_reg[3]) # !C1_bus_reg[6] & (!C1_state.bit4 # !C1_bus_reg[3]);

--C1L6 is uart_emitter:uart_emitter_a|Select~148
--operation mode is normal

C1L6 = C1_bus_reg[6] & !C1_state.bit7 & (!C1_state.bit4 # !C1_bus_reg[3]) # !C1_bus_reg[6] & (!C1_state.bit4 # !C1_bus_reg[3]);


--C1_bus_reg[5] is uart_emitter:uart_emitter_a|bus_reg[5]
--operation mode is normal

C1_bus_reg[5]_lut_out = date_bus[5];
C1_bus_reg[5] = DFFE(C1_bus_reg[5]_lut_out, F1_temp0[2], , , C1L16);


--C1_bus_reg[1] is uart_emitter:uart_emitter_a|bus_reg[1]
--operation mode is normal

C1_bus_reg[1]_lut_out = date_bus[1];
C1_bus_reg[1] = DFFE(C1_bus_reg[1]_lut_out, F1_temp0[2], , , C1L16);


--C1L5 is uart_emitter:uart_emitter_a|Select~146
--operation mode is normal

C1L5 = (C1_bus_reg[5] & !C1_state.bit6 & (!C1_state.bit2 # !C1_bus_reg[1]) # !C1_bus_reg[5] & (!C1_state.bit2 # !C1_bus_reg[1])) & CASCADE(C1L6);


--sel_baud_rate[0] is sel_baud_rate[0]
--operation mode is input

sel_baud_rate[0] = INPUT();


--sel_baud_rate[1] is sel_baud_rate[1]
--operation mode is input

sel_baud_rate[1] = INPUT();


--sel_baud_rate[2] is sel_baud_rate[2]
--operation mode is input

sel_baud_rate[2] = INPUT();


--rest is rest
--operation mode is input

rest = INPUT();


--load_bus_reg is load_bus_reg
--operation mode is input

load_bus_reg = INPUT();


--date_bus[0] is date_bus[0]
--operation mode is input

date_bus[0] = INPUT();


--date_bus[2] is date_bus[2]
--operation mode is input

date_bus[2] = INPUT();


--date_bus[4] is date_bus[4]
--operation mode is input

date_bus[4] = INPUT();


--date_bus[7] is date_bus[7]
--operation mode is input

date_bus[7] = INPUT();


--sys_clock is sys_clock
--operation mode is input

sys_clock = INPUT();


--date_bus[6] is date_bus[6]
--operation mode is input

date_bus[6] = INPUT();


--date_bus[3] is date_bus[3]
--operation mode is input

date_bus[3] = INPUT();


--date_bus[5] is date_bus[5]
--operation mode is input

date_bus[5] = INPUT();


--date_bus[1] is date_bus[1]
--operation mode is input

date_bus[1] = INPUT();


--finish_F is finish_F
--operation mode is output

finish_F = OUTPUT(C1_finish_F);


--bit_counter[0] is bit_counter[0]
--operation mode is output

bit_counter[0] = OUTPUT(D1_bit_counter[0]);


--bit_counter[1] is bit_counter[1]
--operation mode is output

bit_counter[1] = OUTPUT(D1_bit_counter[1]);


--bit_counter[2] is bit_counter[2]
--operation mode is output

bit_counter[2] = OUTPUT(D1_bit_counter[2]);


--bit_counter[3] is bit_counter[3]
--operation mode is output

bit_counter[3] = OUTPUT(D1_bit_counter[3]);


--counter[0] is counter[0]
--operation mode is output

counter[0] = OUTPUT(D1_counter[0]);


--counter[1] is counter[1]
--operation mode is output

counter[1] = OUTPUT(D1_counter[1]);


--counter[2] is counter[2]
--operation mode is output

counter[2] = OUTPUT(D1_counter[2]);


--counter[3] is counter[3]
--operation mode is output

counter[3] = OUTPUT(D1_counter[3]);


--bus[0] is bus[0]
--operation mode is output

bus[0] = OUTPUT(D1_bus[0]);


--bus[1] is bus[1]
--operation mode is output

bus[1] = OUTPUT(D1_bus[1]);


--bus[2] is bus[2]
--operation mode is output

bus[2] = OUTPUT(D1_bus[2]);


--bus[3] is bus[3]
--operation mode is output

bus[3] = OUTPUT(D1_bus[3]);


--bus[4] is bus[4]
--operation mode is output

bus[4] = OUTPUT(D1_bus[4]);


--bus[5] is bus[5]
--operation mode is output

bus[5] = OUTPUT(D1_bus[5]);


--bus[6] is bus[6]
--operation mode is output

bus[6] = OUTPUT(D1_bus[6]);


--bus[7] is bus[7]
--operation mode is output

bus[7] = OUTPUT(D1_bus[7]);


--error is error
--operation mode is output

error = OUTPUT(VCC);


--finish_s is finish_s
--operation mode is output

finish_s = OUTPUT(D1_finish_s);


--serial is serial
--operation mode is output

serial = OUTPUT(!C1_serial);


--clock is clock
--operation mode is output

clock = OUTPUT(F1L5);


--sample_clock is sample_clock
--operation mode is output

sample_clock = OUTPUT(F1_temp0[2]);