uart_top.map.eqn

来自「Uart port 是一段不错的」· EQN 代码 · 共 848 行 · 第 1/2 页

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--C1_finish_F is uart_emitter:uart_emitter_a|finish_F
--operation mode is normal

C1_finish_F_lut_out = C1_state.over # C1_finish_F & C1_state.idle;
C1_finish_F = DFFE(C1_finish_F_lut_out, F1_temp0[2], !rest, , );


--D1_bit_counter[0] is uart_receive:uart_receiver_a|bit_counter[0]
--operation mode is normal

D1_bit_counter[0]_lut_out = !D1_bit_counter[0] & (D1_bit_counter[1] # D1_bit_counter[2] # !D1_bit_counter[3]);
D1_bit_counter[0] = DFFE(D1_bit_counter[0]_lut_out, F1L5, !rest, , D1L3);


--D1_bit_counter[1] is uart_receive:uart_receiver_a|bit_counter[1]
--operation mode is normal

D1_bit_counter[1]_lut_out = D1_bit_counter[1] $ (D1_bit_counter[0] & D1_state & A1L35);
D1_bit_counter[1] = DFFE(D1_bit_counter[1]_lut_out, F1L5, !rest, , );


--D1_bit_counter[2] is uart_receive:uart_receiver_a|bit_counter[2]
--operation mode is normal

D1_bit_counter[2]_lut_out = D1_bit_counter[2] $ (D1_bit_counter[1] & D1_bit_counter[0] & D1L3);
D1_bit_counter[2] = DFFE(D1_bit_counter[2]_lut_out, F1L5, !rest, , );


--D1_bit_counter[3] is uart_receive:uart_receiver_a|bit_counter[3]
--operation mode is normal

D1_bit_counter[3]_lut_out = D1_bit_counter[0] & (D1_bit_counter[3] $ (D1_bit_counter[1] & D1_bit_counter[2])) # !D1_bit_counter[0] & D1_bit_counter[3] & (D1_bit_counter[1] # D1_bit_counter[2]);
D1_bit_counter[3] = DFFE(D1_bit_counter[3]_lut_out, F1L5, !rest, , D1L3);


--D1_counter[0] is uart_receive:uart_receiver_a|counter[0]
--operation mode is normal

D1_counter[0]_lut_out = D1_counter[0] $ (C1_serial # D1_state);
D1_counter[0] = DFFE(D1_counter[0]_lut_out, F1L5, !rest, , );


--D1_counter[1] is uart_receive:uart_receiver_a|counter[1]
--operation mode is normal

D1_counter[1]_lut_out = D1_counter[1] $ (D1_counter[0] & (C1_serial # D1_state));
D1_counter[1] = DFFE(D1_counter[1]_lut_out, F1L5, !rest, , );


--D1_counter[2] is uart_receive:uart_receiver_a|counter[2]
--operation mode is normal

D1_counter[2]_lut_out = !D1L33;
D1_counter[2] = DFFE(D1_counter[2]_lut_out, F1L5, !rest, , );


--D1_counter[3] is uart_receive:uart_receiver_a|counter[3]
--operation mode is normal

D1_counter[3]_lut_out = A1L36 & !D1_state & (D1_counter[3] $ C1_serial) # !A1L36 & D1_counter[3];
D1_counter[3] = DFFE(D1_counter[3]_lut_out, F1L5, !rest, , );


--D1_bus[0] is uart_receive:uart_receiver_a|bus[0]
--operation mode is normal

D1_bus[0]_lut_out = D1_bus_reg[0];
D1_bus[0] = DFFE(D1_bus[0]_lut_out, F1L5, , , D1L9);


--D1_bus[1] is uart_receive:uart_receiver_a|bus[1]
--operation mode is normal

D1_bus[1]_lut_out = D1_bus_reg[1];
D1_bus[1] = DFFE(D1_bus[1]_lut_out, F1L5, , , D1L9);


--D1_bus[2] is uart_receive:uart_receiver_a|bus[2]
--operation mode is normal

D1_bus[2]_lut_out = D1_bus_reg[2];
D1_bus[2] = DFFE(D1_bus[2]_lut_out, F1L5, , , D1L9);


--D1_bus[3] is uart_receive:uart_receiver_a|bus[3]
--operation mode is normal

D1_bus[3]_lut_out = D1_bus_reg[3];
D1_bus[3] = DFFE(D1_bus[3]_lut_out, F1L5, , , D1L9);


--D1_bus[4] is uart_receive:uart_receiver_a|bus[4]
--operation mode is normal

D1_bus[4]_lut_out = D1_bus_reg[4];
D1_bus[4] = DFFE(D1_bus[4]_lut_out, F1L5, , , D1L9);


--D1_bus[5] is uart_receive:uart_receiver_a|bus[5]
--operation mode is normal

D1_bus[5]_lut_out = D1_bus_reg[5];
D1_bus[5] = DFFE(D1_bus[5]_lut_out, F1L5, , , D1L9);


--D1_bus[6] is uart_receive:uart_receiver_a|bus[6]
--operation mode is normal

D1_bus[6]_lut_out = D1_bus_reg[6];
D1_bus[6] = DFFE(D1_bus[6]_lut_out, F1L5, , , D1L9);


--D1_bus[7] is uart_receive:uart_receiver_a|bus[7]
--operation mode is normal

D1_bus[7]_lut_out = D1_bus_reg[7];
D1_bus[7] = DFFE(D1_bus[7]_lut_out, F1L5, , , D1L9);


--D1_finish_s is uart_receive:uart_receiver_a|finish_s
--operation mode is normal

D1_finish_s_lut_out = D1_finish_s # D1L3 & A1L37 & !C1_serial;
D1_finish_s = DFFE(D1_finish_s_lut_out, F1L5, !rest, , );


--C1_serial is uart_emitter:uart_emitter_a|serial
--operation mode is normal

C1_serial_lut_out = !C1L1 & !C1L2 & !C1L3 & C1L5;
C1_serial = DFFE(C1_serial_lut_out, F1_temp0[2], !rest, , );


--F1_temp[5] is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[5]
--operation mode is arithmetic

F1_temp[5]_lut_out = F1_temp[5] $ (F1L20);
F1_temp[5] = DFFE(F1_temp[5]_lut_out, E1_temp[3], !rest, , );

--F1L22 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[5]~57
--operation mode is arithmetic

F1L22 = CARRY(!F1L20 # !F1_temp[5]);


--F1_temp[6] is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[6]
--operation mode is arithmetic

F1_temp[6]_lut_out = F1_temp[6] $ (!F1L22);
F1_temp[6] = DFFE(F1_temp[6]_lut_out, E1_temp[3], !rest, , );

--F1L24 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[6]~60
--operation mode is arithmetic

F1L24 = CARRY(F1_temp[6] & (!F1L22));


--F1_temp[4] is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[4]
--operation mode is arithmetic

F1_temp[4]_lut_out = F1_temp[4] $ (!F1L18);
F1_temp[4] = DFFE(F1_temp[4]_lut_out, E1_temp[3], !rest, , );

--F1L20 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[4]~63
--operation mode is arithmetic

F1L20 = CARRY(F1_temp[4] & (!F1L18));


--F1L1 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~30
--operation mode is normal

F1L1 = sel_baud_rate[0] & (sel_baud_rate[1]) # !sel_baud_rate[0] & (sel_baud_rate[1] & F1_temp[6] # !sel_baud_rate[1] & (F1_temp[4]));


--F1_temp[7] is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[7]
--operation mode is normal

F1_temp[7]_lut_out = F1_temp[7] $ (F1L24);
F1_temp[7] = DFFE(F1_temp[7]_lut_out, E1_temp[3], !rest, , );


--F1L2 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~31
--operation mode is normal

F1L2 = sel_baud_rate[0] & (F1L1 & (F1_temp[7]) # !F1L1 & F1_temp[5]) # !sel_baud_rate[0] & (F1L1);


--F1_temp[2] is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[2]
--operation mode is arithmetic

F1_temp[2]_lut_out = F1_temp[2] $ (!F1L14);
F1_temp[2] = DFFE(F1_temp[2]_lut_out, E1_temp[3], !rest, , );

--F1L16 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[2]~69
--operation mode is arithmetic

F1L16 = CARRY(F1_temp[2] & (!F1L14));


--F1_temp[1] is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[1]
--operation mode is arithmetic

F1_temp[1]_lut_out = F1_temp[1] $ (F1L12);
F1_temp[1] = DFFE(F1_temp[1]_lut_out, E1_temp[3], !rest, , );

--F1L14 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[1]~72
--operation mode is arithmetic

F1L14 = CARRY(!F1L12 # !F1_temp[1]);


--F1_temp[0] is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[0]
--operation mode is arithmetic

F1_temp[0]_lut_out = !F1_temp[0];
F1_temp[0] = DFFE(F1_temp[0]_lut_out, E1_temp[3], !rest, , );

--F1L12 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[0]~75
--operation mode is arithmetic

F1L12 = CARRY(F1_temp[0]);


--F1L3 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32
--operation mode is normal

F1L3 = sel_baud_rate[1] & (sel_baud_rate[0]) # !sel_baud_rate[1] & (sel_baud_rate[0] & F1_temp[1] # !sel_baud_rate[0] & (F1_temp[0]));


--F1_temp[3] is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[3]
--operation mode is arithmetic

F1_temp[3]_lut_out = F1_temp[3] $ (F1L16);
F1_temp[3] = DFFE(F1_temp[3]_lut_out, E1_temp[3], !rest, , );

--F1L18 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[3]~78
--operation mode is arithmetic

F1L18 = CARRY(!F1L16 # !F1_temp[3]);


--F1L4 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33
--operation mode is normal

F1L4 = sel_baud_rate[1] & (F1L3 & (F1_temp[3]) # !F1L3 & F1_temp[2]) # !sel_baud_rate[1] & (F1L3);


--F1L5 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34
--operation mode is normal

F1L5 = sel_baud_rate[2] & F1L2 # !sel_baud_rate[2] & (F1L4);


--F1_temp0[2] is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[2]
--operation mode is normal

F1_temp0[2]_lut_out = F1_temp0[2] $ (F1_temp0[1] & F1_temp0[0]);
F1_temp0[2] = DFFE(F1_temp0[2]_lut_out, F1L5, !rest, , );


--C1_state.over is uart_emitter:uart_emitter_a|state.over
--operation mode is normal

C1_state.over_lut_out = C1_state.bit9;
C1_state.over = DFFE(C1_state.over_lut_out, F1_temp0[2], !rest, , );


--C1_state.idle is uart_emitter:uart_emitter_a|state.idle
--operation mode is normal

C1_state.idle_lut_out = !C1_state.over & (C1_state.idle # load_bus_reg);
C1_state.idle = DFFE(C1_state.idle_lut_out, F1_temp0[2], !rest, , );


--D1_state is uart_receive:uart_receiver_a|state
--operation mode is normal

D1_state_lut_out = D1_state & D1L37 # !D1_state & (A1L38 & C1_serial);
D1_state = DFFE(D1_state_lut_out, F1L5, !rest, , );


--A1L35 is rtl~108
--operation mode is normal

A1L35 = D1_counter[2] & D1_counter[0] & D1_counter[1] & !D1_counter[3];


--D1L3 is uart_receive:uart_receiver_a|bit_counter[0]~163
--operation mode is normal

D1L3 = D1_state & A1L35;


--A1L36 is rtl~109
--operation mode is normal

A1L36 = D1_counter[2] & D1_counter[0] & D1_counter[1];


--D1_bus_reg[0] is uart_receive:uart_receiver_a|bus_reg[0]
--operation mode is normal

D1_bus_reg[0]_lut_out = D1_bus_reg[1];
D1_bus_reg[0] = DFFE(D1_bus_reg[0]_lut_out, F1L5, , , D1L19);


--A1L37 is rtl~110
--operation mode is normal

A1L37 = D1_bit_counter[3] & !D1_bit_counter[0] & !D1_bit_counter[1] & !D1_bit_counter[2];


--D1L9 is uart_receive:uart_receiver_a|bus[0]~15
--operation mode is normal

D1L9 = D1L3 & A1L37 & !rest & !C1_serial;


--D1_bus_reg[1] is uart_receive:uart_receiver_a|bus_reg[1]
--operation mode is normal

D1_bus_reg[1]_lut_out = D1_bus_reg[2];
D1_bus_reg[1] = DFFE(D1_bus_reg[1]_lut_out, F1L5, , , D1L19);


--D1_bus_reg[2] is uart_receive:uart_receiver_a|bus_reg[2]
--operation mode is normal

D1_bus_reg[2]_lut_out = D1_bus_reg[3];
D1_bus_reg[2] = DFFE(D1_bus_reg[2]_lut_out, F1L5, , , D1L19);


--D1_bus_reg[3] is uart_receive:uart_receiver_a|bus_reg[3]
--operation mode is normal

D1_bus_reg[3]_lut_out = D1_bus_reg[4];
D1_bus_reg[3] = DFFE(D1_bus_reg[3]_lut_out, F1L5, , , D1L19);


--D1_bus_reg[4] is uart_receive:uart_receiver_a|bus_reg[4]
--operation mode is normal

D1_bus_reg[4]_lut_out = D1_bus_reg[5];
D1_bus_reg[4] = DFFE(D1_bus_reg[4]_lut_out, F1L5, , , D1L19);


--D1_bus_reg[5] is uart_receive:uart_receiver_a|bus_reg[5]
--operation mode is normal

D1_bus_reg[5]_lut_out = D1_bus_reg[6];
D1_bus_reg[5] = DFFE(D1_bus_reg[5]_lut_out, F1L5, , , D1L19);


--D1_bus_reg[6] is uart_receive:uart_receiver_a|bus_reg[6]
--operation mode is normal

D1_bus_reg[6]_lut_out = D1_bus_reg[7];
D1_bus_reg[6] = DFFE(D1_bus_reg[6]_lut_out, F1L5, , , D1L19);


--D1_bus_reg[7] is uart_receive:uart_receiver_a|bus_reg[7]
--operation mode is normal

D1_bus_reg[7]_lut_out = !C1_serial;
D1_bus_reg[7] = DFFE(D1_bus_reg[7]_lut_out, F1L5, , , D1L19);


--C1_bus_reg[0] is uart_emitter:uart_emitter_a|bus_reg[0]
--operation mode is normal

C1_bus_reg[0]_lut_out = date_bus[0];
C1_bus_reg[0] = DFFE(C1_bus_reg[0]_lut_out, F1_temp0[2], , , C1L16);


--C1_bus_reg[2] is uart_emitter:uart_emitter_a|bus_reg[2]
--operation mode is normal

C1_bus_reg[2]_lut_out = date_bus[2];
C1_bus_reg[2] = DFFE(C1_bus_reg[2]_lut_out, F1_temp0[2], , , C1L16);


--C1_state.bit3 is uart_emitter:uart_emitter_a|state.bit3
--operation mode is normal

C1_state.bit3_lut_out = C1_state.bit2;
C1_state.bit3 = DFFE(C1_state.bit3_lut_out, F1_temp0[2], !rest, , );


--C1_state.bit1 is uart_emitter:uart_emitter_a|state.bit1
--operation mode is normal

C1_state.bit1_lut_out = C1_state.bit0;
C1_state.bit1 = DFFE(C1_state.bit1_lut_out, F1_temp0[2], !rest, , );


--C1L1 is uart_emitter:uart_emitter_a|Select~135
--operation mode is normal

C1L1 = C1_bus_reg[0] & (C1_state.bit1 # C1_bus_reg[2] & C1_state.bit3) # !C1_bus_reg[0] & C1_bus_reg[2] & C1_state.bit3;


--C1_bus_reg[4] is uart_emitter:uart_emitter_a|bus_reg[4]
--operation mode is normal

C1_bus_reg[4]_lut_out = date_bus[4];
C1_bus_reg[4] = DFFE(C1_bus_reg[4]_lut_out, F1_temp0[2], , , C1L16);


--C1_bus_reg[7] is uart_emitter:uart_emitter_a|bus_reg[7]
--operation mode is normal