uart_top.tan.rpt

来自「Uart port 是一段不错的」· RPT 代码 · 共 287 行 · 第 1/5 页

; Clock Setup: 'sel_baud_rate[2]' ; N/A                                      ; None          ; 133.32 MHz ( period = 7.501 ns ) ; uart_emitter:uart_emitter_a|serial     ; uart_receive:uart_receiver_a|bus[5]     ; sel_baud_rate[2] ; sel_baud_rate[2] ; 0            ;
; Clock Hold: 'sys_clock'         ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; uart_emitter:uart_emitter_a|state.bit5 ; uart_emitter:uart_emitter_a|state.bit6  ; sys_clock        ; sys_clock        ; 54           ;
; Clock Hold: 'sel_baud_rate[0]'  ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; uart_emitter:uart_emitter_a|state.bit5 ; uart_emitter:uart_emitter_a|state.bit6  ; sel_baud_rate[0] ; sel_baud_rate[0] ; 18           ;
; Clock Hold: 'sel_baud_rate[1]'  ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; uart_emitter:uart_emitter_a|state.bit5 ; uart_emitter:uart_emitter_a|state.bit6  ; sel_baud_rate[1] ; sel_baud_rate[1] ; 18           ;
; Total number of failed paths    ;                                          ;               ;                                  ;                                        ;                                         ;                  ;                  ; 90           ;
+---------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------------------+-----------------------------------------+------------------+------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP20K30ETC144-1    ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                              ;
+------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name  ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; sys_clock        ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; sel_baud_rate[1] ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; sel_baud_rate[0] ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; sel_baud_rate[2] ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'sys_clock'                                                                                                                                                                                                                                                                               ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------+---------------------------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                        ; To                                          ; From Clock ; To Clock  ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------+---------------------------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 115.17 MHz ( period = 8.683 ns )                    ; uart_emitter:uart_emitter_a|serial          ; uart_receive:uart_receiver_a|bus[5]         ; sys_clock  ; sys_clock ; None                        ; None                      ; 2.364 ns                ;
; N/A                                     ; 115.30 MHz ( period = 8.673 ns )                    ; uart_emitter:uart_emitter_a|serial          ; uart_receive:uart_receiver_a|bus[7]         ; sys_clock  ; sys_clock ; None                        ; None                      ; 2.364 ns                ;
; N/A                                     ; 115.30 MHz ( period = 8.673 ns )                    ; uart_emitter:uart_emitter_a|serial          ; uart_receive:uart_receiver_a|bus[6]         ; sys_clock  ; sys_clock ; None                        ; None                      ; 2.364 ns                ;
; N/A                                     ; 115.30 MHz ( period = 8.673 ns )                    ; uart_emitter:uart_emitter_a|serial          ; uart_receive:uart_receiver_a|bus[4]         ; sys_clock  ; sys_clock ; None                        ; None                      ; 2.364 ns                ;
; N/A                                     ; 115.30 MHz ( period = 8.673 ns )                    ; uart_emitter:uart_emitter_a|serial          ; uart_receive:uart_receiver_a|bus[3]         ; sys_clock  ; sys_clock ; None                        ; None                      ; 2.364 ns                ;
; N/A                                     ; 115.30 MHz ( period = 8.673 ns )                    ; uart_emitter:uart_emitter_a|serial          ; uart_receive:uart_receiver_a|bus[2]         ; sys_clock  ; sys_clock ; None                        ; None                      ; 2.364 ns                ;
; N/A                                     ; 115.30 MHz ( period = 8.673 ns )                    ; uart_emitter:uart_emitter_a|serial          ; uart_receive:uart_receiver_a|bus[1]         ; sys_clock  ; sys_clock ; None                        ; None                      ; 2.364 ns                ;
; N/A                                     ; 115.30 MHz ( period = 8.673 ns )                    ; uart_emitter:uart_emitter_a|serial          ; uart_receive:uart_receiver_a|bus[0]         ; sys_clock  ; sys_clock ; None                        ; None                      ; 2.364 ns                ;