uart_top.fit.eqn

Uart port 是一段不错的

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--C1_finish_F is uart_emitter:uart_emitter_a|finish_F at LC3_9_E2
--operation mode is normal

C1_finish_F_lut_out = C1_state.over # C1_state.idle & C1_finish_F;
C1_finish_F = DFFE(C1_finish_F_lut_out, GLOBAL(F1_temp0[2]), !GLOBAL(rest), , );


--D1_bit_counter[0] is uart_receive:uart_receiver_a|bit_counter[0] at LC2_6_E2
--operation mode is normal

D1_bit_counter[0]_lut_out = !D1_bit_counter[0] & (D1_bit_counter[2] # D1_bit_counter[1] # !D1_bit_counter[3]);
D1_bit_counter[0] = DFFE(D1_bit_counter[0]_lut_out, GLOBAL(F1L5), !GLOBAL(rest), , D1L3);


--D1_bit_counter[1] is uart_receive:uart_receiver_a|bit_counter[1] at LC10_6_E2
--operation mode is normal

D1_bit_counter[1]_lut_out = D1_bit_counter[1] $ (D1_state & D1_bit_counter[0] & A1L35);
D1_bit_counter[1] = DFFE(D1_bit_counter[1]_lut_out, GLOBAL(F1L5), !GLOBAL(rest), , );


--D1_bit_counter[2] is uart_receive:uart_receiver_a|bit_counter[2] at LC1_6_E2
--operation mode is normal

D1_bit_counter[2]_lut_out = D1_bit_counter[2] $ (D1_bit_counter[0] & D1L3 & D1_bit_counter[1]);
D1_bit_counter[2] = DFFE(D1_bit_counter[2]_lut_out, GLOBAL(F1L5), !GLOBAL(rest), , );


--D1_bit_counter[3] is uart_receive:uart_receiver_a|bit_counter[3] at LC5_6_E2
--operation mode is normal

D1_bit_counter[3]_lut_out = D1_bit_counter[2] & (D1_bit_counter[3] $ (D1_bit_counter[1] & D1_bit_counter[0])) # !D1_bit_counter[2] & D1_bit_counter[3] & (D1_bit_counter[1] # D1_bit_counter[0]);
D1_bit_counter[3] = DFFE(D1_bit_counter[3]_lut_out, GLOBAL(F1L5), !GLOBAL(rest), , D1L3);


--D1_counter[0] is uart_receive:uart_receiver_a|counter[0] at LC5_7_E2
--operation mode is normal

D1_counter[0]_lut_out = D1_counter[0] $ (D1_state # C1_serial);
D1_counter[0] = DFFE(D1_counter[0]_lut_out, GLOBAL(F1L5), !GLOBAL(rest), , );


--D1_counter[1] is uart_receive:uart_receiver_a|counter[1] at LC6_7_E2
--operation mode is normal

D1_counter[1]_lut_out = D1_counter[1] $ (D1_counter[0] & (D1_state # C1_serial));
D1_counter[1] = DFFE(D1_counter[1]_lut_out, GLOBAL(F1L5), !GLOBAL(rest), , );


--D1_counter[2] is uart_receive:uart_receiver_a|counter[2] at LC7_7_E2
--operation mode is normal

D1_counter[2]_lut_out = !D1L33;
D1_counter[2] = DFFE(D1_counter[2]_lut_out, GLOBAL(F1L5), !GLOBAL(rest), , );


--D1_counter[3] is uart_receive:uart_receiver_a|counter[3] at LC9_7_E2
--operation mode is normal

D1_counter[3]_lut_out = A1L36 & !D1_state & (D1_counter[3] $ C1_serial) # !A1L36 & D1_counter[3];
D1_counter[3] = DFFE(D1_counter[3]_lut_out, GLOBAL(F1L5), !GLOBAL(rest), , );


--D1_bus[0] is uart_receive:uart_receiver_a|bus[0] at LC8_4_E2
--operation mode is normal

D1_bus[0]_lut_out = D1_bus_reg[0];
D1_bus[0] = DFFE(D1_bus[0]_lut_out, GLOBAL(F1L5), , , D1L9);


--D1_bus[1] is uart_receive:uart_receiver_a|bus[1] at LC10_4_E2
--operation mode is normal

D1_bus[1]_lut_out = D1_bus_reg[1];
D1_bus[1] = DFFE(D1_bus[1]_lut_out, GLOBAL(F1L5), , , D1L9);


--D1_bus[2] is uart_receive:uart_receiver_a|bus[2] at LC9_4_E2
--operation mode is normal

D1_bus[2]_lut_out = D1_bus_reg[2];
D1_bus[2] = DFFE(D1_bus[2]_lut_out, GLOBAL(F1L5), , , D1L9);


--D1_bus[3] is uart_receive:uart_receiver_a|bus[3] at LC6_4_E2
--operation mode is normal

D1_bus[3]_lut_out = D1_bus_reg[3];
D1_bus[3] = DFFE(D1_bus[3]_lut_out, GLOBAL(F1L5), , , D1L9);


--D1_bus[4] is uart_receive:uart_receiver_a|bus[4] at LC7_4_E2
--operation mode is normal

D1_bus[4]_lut_out = D1_bus_reg[4];
D1_bus[4] = DFFE(D1_bus[4]_lut_out, GLOBAL(F1L5), , , D1L9);


--D1_bus[5] is uart_receive:uart_receiver_a|bus[5] at LC10_5_E2
--operation mode is normal

D1_bus[5]_lut_out = D1_bus_reg[5];
D1_bus[5] = DFFE(D1_bus[5]_lut_out, GLOBAL(F1L5), , , D1L9);


--D1_bus[6] is uart_receive:uart_receiver_a|bus[6] at LC4_4_E2
--operation mode is normal

D1_bus[6]_lut_out = D1_bus_reg[6];
D1_bus[6] = DFFE(D1_bus[6]_lut_out, GLOBAL(F1L5), , , D1L9);


--D1_bus[7] is uart_receive:uart_receiver_a|bus[7] at LC5_4_E2
--operation mode is normal

D1_bus[7]_lut_out = D1_bus_reg[7];
D1_bus[7] = DFFE(D1_bus[7]_lut_out, GLOBAL(F1L5), , , D1L9);


--D1_finish_s is uart_receive:uart_receiver_a|finish_s at LC9_6_E2
--operation mode is normal

D1_finish_s_lut_out = D1_finish_s # A1L37 & D1L3 & !C1_serial;
D1_finish_s = DFFE(D1_finish_s_lut_out, GLOBAL(F1L5), !GLOBAL(rest), , );


--C1_serial is uart_emitter:uart_emitter_a|serial at LC10_7_E2
--operation mode is normal

C1_serial_lut_out = C1L5 & !C1L3 & !C1L1 & !C1L2;
C1_serial = DFFE(C1_serial_lut_out, GLOBAL(F1_temp0[2]), !GLOBAL(rest), , );


--F1_temp[5] is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[5] at LC7_1_D1
--operation mode is arithmetic

F1_temp[5]_lut_out = F1_temp[5] $ F1L20;
F1_temp[5] = DFFE(F1_temp[5]_lut_out, GLOBAL(E1_temp[3]), !GLOBAL(rest), , );

--F1L22 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[5]~57 at LC7_1_D1
--operation mode is arithmetic

F1L22 = CARRY(!F1L20 # !F1_temp[5]);


--F1_temp[6] is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[6] at LC8_1_D1
--operation mode is arithmetic

F1_temp[6]_lut_out = F1_temp[6] $ !F1L22;
F1_temp[6] = DFFE(F1_temp[6]_lut_out, GLOBAL(E1_temp[3]), !GLOBAL(rest), , );

--F1L24 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[6]~60 at LC8_1_D1
--operation mode is arithmetic

F1L24 = CARRY(F1_temp[6] & !F1L22);


--F1_temp[4] is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[4] at LC6_1_D1
--operation mode is arithmetic

F1_temp[4]_lut_out = F1_temp[4] $ !F1L18;
F1_temp[4] = DFFE(F1_temp[4]_lut_out, GLOBAL(E1_temp[3]), !GLOBAL(rest), , );

--F1L20 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[4]~63 at LC6_1_D1
--operation mode is arithmetic

F1L20 = CARRY(F1_temp[4] & !F1L18);


--F1L1 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~30 at LC3_2_D1
--operation mode is normal

F1L1 = sel_baud_rate[1] & (F1_temp[6] # sel_baud_rate[0]) # !sel_baud_rate[1] & (F1_temp[4] & !sel_baud_rate[0]);


--F1_temp[7] is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[7] at LC9_1_D1
--operation mode is normal

F1_temp[7]_lut_out = F1L24 $ F1_temp[7];
F1_temp[7] = DFFE(F1_temp[7]_lut_out, GLOBAL(E1_temp[3]), !GLOBAL(rest), , );


--F1L2 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~31 at LC1_2_D1
--operation mode is normal

F1L2 = sel_baud_rate[0] & (F1L1 & F1_temp[7] # !F1L1 & (F1_temp[5])) # !sel_baud_rate[0] & (F1L1);


--F1_temp[2] is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[2] at LC4_1_D1
--operation mode is arithmetic

F1_temp[2]_lut_out = F1_temp[2] $ !F1L14;
F1_temp[2] = DFFE(F1_temp[2]_lut_out, GLOBAL(E1_temp[3]), !GLOBAL(rest), , );

--F1L16 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[2]~69 at LC4_1_D1
--operation mode is arithmetic

F1L16 = CARRY(F1_temp[2] & !F1L14);


--F1_temp[1] is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[1] at LC3_1_D1
--operation mode is arithmetic

F1_temp[1]_lut_out = F1_temp[1] $ F1L12;
F1_temp[1] = DFFE(F1_temp[1]_lut_out, GLOBAL(E1_temp[3]), !GLOBAL(rest), , );

--F1L14 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[1]~72 at LC3_1_D1
--operation mode is arithmetic

F1L14 = CARRY(!F1L12 # !F1_temp[1]);


--F1_temp[0] is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[0] at LC2_1_D1
--operation mode is arithmetic

F1_temp[0]_lut_out = !F1_temp[0];
F1_temp[0] = DFFE(F1_temp[0]_lut_out, GLOBAL(E1_temp[3]), !GLOBAL(rest), , );

--F1L12 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[0]~75 at LC2_1_D1
--operation mode is arithmetic

F1L12 = CARRY(F1_temp[0]);


--F1L3 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32 at LC7_2_D1
--operation mode is normal

F1L3 = sel_baud_rate[1] & (sel_baud_rate[0]) # !sel_baud_rate[1] & (sel_baud_rate[0] & F1_temp[1] # !sel_baud_rate[0] & (F1_temp[0]));


--F1_temp[3] is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[3] at LC5_1_D1
--operation mode is arithmetic

F1_temp[3]_lut_out = F1_temp[3] $ F1L16;
F1_temp[3] = DFFE(F1_temp[3]_lut_out, GLOBAL(E1_temp[3]), !GLOBAL(rest), , );

--F1L18 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[3]~78 at LC5_1_D1
--operation mode is arithmetic

F1L18 = CARRY(!F1L16 # !F1_temp[3]);


--F1L4 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 at LC10_2_D1
--operation mode is normal

F1L4 = sel_baud_rate[1] & (F1L3 & F1_temp[3] # !F1L3 & (F1_temp[2])) # !sel_baud_rate[1] & (F1L3);


--F1L5 is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 at LC10_1_D1
--operation mode is normal

F1L5 = sel_baud_rate[2] & (F1L2) # !sel_baud_rate[2] & F1L4;


--F1_temp0[2] is uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[2] at LC5_2_E1
--operation mode is normal

F1_temp0[2]_lut_out = F1_temp0[2] $ (F1_temp0[0] & F1_temp0[1]);
F1_temp0[2] = DFFE(F1_temp0[2]_lut_out, GLOBAL(F1L5), !GLOBAL(rest), , );


--C1_state.over is uart_emitter:uart_emitter_a|state.over at LC4_9_E2
--operation mode is normal

C1_state.over_lut_out = C1_state.bit9;
C1_state.over = DFFE(C1_state.over_lut_out, GLOBAL(F1_temp0[2]), !GLOBAL(rest), , );


--C1_state.idle is uart_emitter:uart_emitter_a|state.idle at LC5_9_E2
--operation mode is normal

C1_state.idle_lut_out = !C1_state.over & (C1_state.idle # load_bus_reg);
C1_state.idle = DFFE(C1_state.idle_lut_out, GLOBAL(F1_temp0[2]), !GLOBAL(rest), , );


--D1_state is uart_receive:uart_receiver_a|state at LC3_6_E2
--operation mode is normal

D1_state_lut_out = D1_state & (D1L37) # !D1_state & A1L38 & (C1_serial);
D1_state = DFFE(D1_state_lut_out, GLOBAL(F1L5), !GLOBAL(rest), , );


--A1L35 is rtl~108 at LC4_7_E2
--operation mode is normal

A1L35 = D1_counter[0] & D1_counter[2] & !D1_counter[3] & D1_counter[1];


--D1L3 is uart_receive:uart_receiver_a|bit_counter[0]~163 at LC7_6_E2
--operation mode is normal

D1L3 = D1_state & A1L35;


--A1L36 is rtl~109 at LC8_7_E2
--operation mode is normal

A1L36 = D1_counter[2] & (D1_counter[0] & D1_counter[1]);


--D1_bus_reg[0] is uart_receive:uart_receiver_a|bus_reg[0] at LC3_5_E2
--operation mode is normal

D1_bus_reg[0]_lut_out = D1_bus_reg[1];
D1_bus_reg[0] = DFFE(D1_bus_reg[0]_lut_out, GLOBAL(F1L5), , , D1L19);


--A1L37 is rtl~110 at LC6_6_E2
--operation mode is normal

A1L37 = !D1_bit_counter[0] & !D1_bit_counter[1] & !D1_bit_counter[2] & D1_bit_counter[3];


--D1L9 is uart_receive:uart_receiver_a|bus[0]~15 at LC9_5_E2
--operation mode is normal

D1L9 = !rest & D1L3 & A1L37 & !C1_serial;


--D1_bus_reg[1] is uart_receive:uart_receiver_a|bus_reg[1] at LC8_5_E2
--operation mode is normal

D1_bus_reg[1]_lut_out = D1_bus_reg[2];
D1_bus_reg[1] = DFFE(D1_bus_reg[1]_lut_out, GLOBAL(F1L5), , , D1L19);


--D1_bus_reg[2] is uart_receive:uart_receiver_a|bus_reg[2] at LC2_4_E2
--operation mode is normal

D1_bus_reg[2]_lut_out = D1_bus_reg[3];
D1_bus_reg[2] = DFFE(D1_bus_reg[2]_lut_out, GLOBAL(F1L5), , , D1L19);


--D1_bus_reg[3] is uart_receive:uart_receiver_a|bus_reg[3] at LC1_5_E2
--operation mode is normal

D1_bus_reg[3]_lut_out = D1_bus_reg[4];
D1_bus_reg[3] = DFFE(D1_bus_reg[3]_lut_out, GLOBAL(F1L5), , , D1L19);


--D1_bus_reg[4] is uart_receive:uart_receiver_a|bus_reg[4] at LC4_5_E2
--operation mode is normal

D1_bus_reg[4]_lut_out = D1_bus_reg[5];
D1_bus_reg[4] = DFFE(D1_bus_reg[4]_lut_out, GLOBAL(F1L5), , , D1L19);


--D1_bus_reg[5] is uart_receive:uart_receiver_a|bus_reg[5] at LC5_5_E2
--operation mode is normal

D1_bus_reg[5]_lut_out = D1_bus_reg[6];
D1_bus_reg[5] = DFFE(D1_bus_reg[5]_lut_out, GLOBAL(F1L5), , , D1L19);


--D1_bus_reg[6] is uart_receive:uart_receiver_a|bus_reg[6] at LC7_5_E2
--operation mode is normal

D1_bus_reg[6]_lut_out = D1_bus_reg[7];
D1_bus_reg[6] = DFFE(D1_bus_reg[6]_lut_out, GLOBAL(F1L5), , , D1L19);


--D1_bus_reg[7] is uart_receive:uart_receiver_a|bus_reg[7] at LC6_5_E2
--operation mode is normal

D1_bus_reg[7]_lut_out = !C1_serial;
D1_bus_reg[7] = DFFE(D1_bus_reg[7]_lut_out, GLOBAL(F1L5), , , D1L19);


--C1_bus_reg[0] is uart_emitter:uart_emitter_a|bus_reg[0] at LC3_2_E2
--operation mode is normal

C1_bus_reg[0]_lut_out = date_bus[0];
C1_bus_reg[0] = DFFE(C1_bus_reg[0]_lut_out, GLOBAL(F1_temp0[2]), , , C1L16);


--C1_bus_reg[2] is uart_emitter:uart_emitter_a|bus_reg[2] at LC5_2_E2
--operation mode is normal

C1_bus_reg[2]_lut_out = date_bus[2];
C1_bus_reg[2] = DFFE(C1_bus_reg[2]_lut_out, GLOBAL(F1_temp0[2]), , , C1L16);


--C1_state.bit3 is uart_emitter:uart_emitter_a|state.bit3 at LC4_2_E2
--operation mode is normal

C1_state.bit3_lut_out = C1_state.bit2;
C1_state.bit3 = DFFE(C1_state.bit3_lut_out, GLOBAL(F1_temp0[2]), !GLOBAL(rest), , );


--C1_state.bit1 is uart_emitter:uart_emitter_a|state.bit1 at LC6_2_E2
--operation mode is normal

C1_state.bit1_lut_out = C1_state.bit0;
C1_state.bit1 = DFFE(C1_state.bit1_lut_out, GLOBAL(F1_temp0[2]), !GLOBAL(rest), , );


--C1L1 is uart_emitter:uart_emitter_a|Select~135 at LC10_2_E2
--operation mode is normal

C1L1 = C1_state.bit1 & (C1_bus_reg[0] # C1_bus_reg[2] & C1_state.bit3) # !C1_state.bit1 & C1_bus_reg[2] & C1_state.bit3;


--C1_bus_reg[4] is uart_emitter:uart_emitter_a|bus_reg[4] at LC8_8_E2
--operation mode is normal

C1_bus_reg[4]_lut_out = date_bus[4];
C1_bus_reg[4] = DFFE(C1_bus_reg[4]_lut_out, GLOBAL(F1_temp0[2]), , , C1L16);


--C1_bus_reg[7] is uart_emitter:uart_emitter_a|bus_reg[7] at LC3_8_E2
--operation mode is normal