uart_clk.map.eqn

Uart port 是一段不错的

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--C1_temp[5] is divide_by_256:divide_256|temp[5]
--operation mode is arithmetic

C1_temp[5]_lut_out = C1_temp[5] $ (C1L20);
C1_temp[5] = DFFE(C1_temp[5]_lut_out, B1_temp[3], !rest, , );

--C1L22 is divide_by_256:divide_256|temp[5]~57
--operation mode is arithmetic

C1L22 = CARRY(!C1L20 # !C1_temp[5]);


--C1_temp[6] is divide_by_256:divide_256|temp[6]
--operation mode is arithmetic

C1_temp[6]_lut_out = C1_temp[6] $ (!C1L22);
C1_temp[6] = DFFE(C1_temp[6]_lut_out, B1_temp[3], !rest, , );

--C1L24 is divide_by_256:divide_256|temp[6]~60
--operation mode is arithmetic

C1L24 = CARRY(C1_temp[6] & (!C1L22));


--C1_temp[4] is divide_by_256:divide_256|temp[4]
--operation mode is arithmetic

C1_temp[4]_lut_out = C1_temp[4] $ (!C1L18);
C1_temp[4] = DFFE(C1_temp[4]_lut_out, B1_temp[3], !rest, , );

--C1L20 is divide_by_256:divide_256|temp[4]~63
--operation mode is arithmetic

C1L20 = CARRY(C1_temp[4] & (!C1L18));


--C1L1 is divide_by_256:divide_256|clock~30
--operation mode is normal

C1L1 = sel_baud_rate[0] & (sel_baud_rate[1]) # !sel_baud_rate[0] & (sel_baud_rate[1] & C1_temp[6] # !sel_baud_rate[1] & (C1_temp[4]));


--C1_temp[7] is divide_by_256:divide_256|temp[7]
--operation mode is normal

C1_temp[7]_lut_out = C1_temp[7] $ (C1L24);
C1_temp[7] = DFFE(C1_temp[7]_lut_out, B1_temp[3], !rest, , );


--C1L2 is divide_by_256:divide_256|clock~31
--operation mode is normal

C1L2 = sel_baud_rate[0] & (C1L1 & (C1_temp[7]) # !C1L1 & C1_temp[5]) # !sel_baud_rate[0] & (C1L1);


--C1_temp[2] is divide_by_256:divide_256|temp[2]
--operation mode is arithmetic

C1_temp[2]_lut_out = C1_temp[2] $ (!C1L14);
C1_temp[2] = DFFE(C1_temp[2]_lut_out, B1_temp[3], !rest, , );

--C1L16 is divide_by_256:divide_256|temp[2]~69
--operation mode is arithmetic

C1L16 = CARRY(C1_temp[2] & (!C1L14));


--C1_temp[1] is divide_by_256:divide_256|temp[1]
--operation mode is arithmetic

C1_temp[1]_lut_out = C1_temp[1] $ (C1L12);
C1_temp[1] = DFFE(C1_temp[1]_lut_out, B1_temp[3], !rest, , );

--C1L14 is divide_by_256:divide_256|temp[1]~72
--operation mode is arithmetic

C1L14 = CARRY(!C1L12 # !C1_temp[1]);


--C1_temp[0] is divide_by_256:divide_256|temp[0]
--operation mode is arithmetic

C1_temp[0]_lut_out = !C1_temp[0];
C1_temp[0] = DFFE(C1_temp[0]_lut_out, B1_temp[3], !rest, , );

--C1L12 is divide_by_256:divide_256|temp[0]~75
--operation mode is arithmetic

C1L12 = CARRY(C1_temp[0]);


--C1L3 is divide_by_256:divide_256|clock~32
--operation mode is normal

C1L3 = sel_baud_rate[1] & (sel_baud_rate[0]) # !sel_baud_rate[1] & (sel_baud_rate[0] & C1_temp[1] # !sel_baud_rate[0] & (C1_temp[0]));


--C1_temp[3] is divide_by_256:divide_256|temp[3]
--operation mode is arithmetic

C1_temp[3]_lut_out = C1_temp[3] $ (C1L16);
C1_temp[3] = DFFE(C1_temp[3]_lut_out, B1_temp[3], !rest, , );

--C1L18 is divide_by_256:divide_256|temp[3]~78
--operation mode is arithmetic

C1L18 = CARRY(!C1L16 # !C1_temp[3]);


--C1L4 is divide_by_256:divide_256|clock~33
--operation mode is normal

C1L4 = sel_baud_rate[1] & (C1L3 & (C1_temp[3]) # !C1L3 & C1_temp[2]) # !sel_baud_rate[1] & (C1L3);


--C1L5 is divide_by_256:divide_256|clock~34
--operation mode is normal

C1L5 = sel_baud_rate[2] & C1L2 # !sel_baud_rate[2] & (C1L4);


--C1_temp0[2] is divide_by_256:divide_256|temp0[2]
--operation mode is normal

C1_temp0[2]_lut_out = C1_temp0[2] $ (C1_temp0[1] & C1_temp0[0]);
C1_temp0[2] = DFFE(C1_temp0[2]_lut_out, C1L5, !rest, , );


--B1_temp[3] is divide_by_13:divide_13|temp[3]
--operation mode is normal

B1_temp[3]_lut_out = B1_temp[3] & (B1_temp[1] $ B1_temp[0] # !B1_temp[2]) # !B1_temp[3] & B1_temp[1] & B1_temp[0] & B1_temp[2];
B1_temp[3] = DFFE(B1_temp[3]_lut_out, sys_clock, !rest, , );


--C1_temp0[1] is divide_by_256:divide_256|temp0[1]
--operation mode is normal

C1_temp0[1]_lut_out = C1_temp0[1] $ C1_temp0[0];
C1_temp0[1] = DFFE(C1_temp0[1]_lut_out, C1L5, !rest, , );


--C1_temp0[0] is divide_by_256:divide_256|temp0[0]
--operation mode is normal

C1_temp0[0]_lut_out = !C1_temp0[0];
C1_temp0[0] = DFFE(C1_temp0[0]_lut_out, C1L5, !rest, , );


--B1_temp[1] is divide_by_13:divide_13|temp[1]
--operation mode is normal

B1_temp[1]_lut_out = B1_temp[1] $ B1_temp[0];
B1_temp[1] = DFFE(B1_temp[1]_lut_out, sys_clock, !rest, , );


--B1_temp[0] is divide_by_13:divide_13|temp[0]
--operation mode is normal

B1_temp[0]_lut_out = !B1_temp[0] & (B1_temp[1] # !B1_temp[2] # !B1_temp[3]);
B1_temp[0] = DFFE(B1_temp[0]_lut_out, sys_clock, !rest, , );


--B1_temp[2] is divide_by_13:divide_13|temp[2]
--operation mode is normal

B1_temp[2]_lut_out = B1_temp[1] & (B1_temp[2] $ B1_temp[0]) # !B1_temp[1] & B1_temp[2] & (B1_temp[0] # !B1_temp[3]);
B1_temp[2] = DFFE(B1_temp[2]_lut_out, sys_clock, !rest, , );


--sel_baud_rate[0] is sel_baud_rate[0]
--operation mode is input

sel_baud_rate[0] = INPUT();


--sel_baud_rate[1] is sel_baud_rate[1]
--operation mode is input

sel_baud_rate[1] = INPUT();


--sel_baud_rate[2] is sel_baud_rate[2]
--operation mode is input

sel_baud_rate[2] = INPUT();


--rest is rest
--operation mode is input

rest = INPUT();


--sys_clock is sys_clock
--operation mode is input

sys_clock = INPUT();


--clock is clock
--operation mode is output

clock = OUTPUT(C1L5);


--sample_clock is sample_clock
--operation mode is output

sample_clock = OUTPUT(C1_temp0[2]);