uart_top.sim.rpt

Uart port 是一段不错的

; |uart_top|date_bus[3]                                               ; |uart_top|date_bus[3]                                               ; data_out0        ;
; |uart_top|date_bus[5]                                               ; |uart_top|date_bus[5]                                               ; data_out0        ;
; |uart_top|date_bus[1]                                               ; |uart_top|date_bus[1]                                               ; data_out0        ;
; |uart_top|counter[3]                                                ; |uart_top|counter[3]                                                ; padio            ;
; |uart_top|bus[3]                                                    ; |uart_top|bus[3]                                                    ; padio            ;
; |uart_top|bus[4]                                                    ; |uart_top|bus[4]                                                    ; padio            ;
; |uart_top|bus[6]                                                    ; |uart_top|bus[6]                                                    ; padio            ;
; |uart_top|error                                                     ; |uart_top|error                                                     ; padio            ;
+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                                                                                     ;
+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------+
; Node Name                                                           ; Output Port Name                                                    ; Output Port Type ;
+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------+
; |uart_top|uart_receive:uart_receiver_a|bus[0]                       ; |uart_top|uart_receive:uart_receiver_a|bus[0]                       ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bus[1]                       ; |uart_top|uart_receive:uart_receiver_a|bus[1]                       ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bus[2]                       ; |uart_top|uart_receive:uart_receiver_a|bus[2]                       ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bus[3]                       ; |uart_top|uart_receive:uart_receiver_a|bus[3]                       ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bus[4]                       ; |uart_top|uart_receive:uart_receiver_a|bus[4]                       ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bus[5]                       ; |uart_top|uart_receive:uart_receiver_a|bus[5]                       ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bus[6]                       ; |uart_top|uart_receive:uart_receiver_a|bus[6]                       ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bus[7]                       ; |uart_top|uart_receive:uart_receiver_a|bus[7]                       ; data_out0        ;
; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~30 ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~30 ; data_out0        ;
; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32 ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32 ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bus_reg[0]                   ; |uart_top|uart_receive:uart_receiver_a|bus_reg[0]                   ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bus_reg[1]                   ; |uart_top|uart_receive:uart_receiver_a|bus_reg[1]                   ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bus_reg[2]                   ; |uart_top|uart_receive:uart_receiver_a|bus_reg[2]                   ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|bus_reg[0]                    ; |uart_top|uart_emitter:uart_emitter_a|bus_reg[0]                    ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|bus_reg[2]                    ; |uart_top|uart_emitter:uart_emitter_a|bus_reg[2]                    ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|bus_reg[4]                    ; |uart_top|uart_emitter:uart_emitter_a|bus_reg[4]                    ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|bus_reg[7]                    ; |uart_top|uart_emitter:uart_emitter_a|bus_reg[7]                    ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|bus_reg[6]                    ; |uart_top|uart_emitter:uart_emitter_a|bus_reg[6]                    ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|bus_reg[3]                    ; |uart_top|uart_emitter:uart_emitter_a|bus_reg[3]                    ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|Select~148                    ; |uart_top|uart_emitter:uart_emitter_a|Select~148                    ; cascout          ;
; |uart_top|uart_emitter:uart_emitter_a|bus_reg[5]                    ; |uart_top|uart_emitter:uart_emitter_a|bus_reg[5]                    ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|bus_reg[1]                    ; |uart_top|uart_emitter:uart_emitter_a|bus_reg[1]                    ; data_out0        ;
; |uart_top|sel_baud_rate[0]                                          ; |uart_top|sel_baud_rate[0]                                          ; data_out0        ;
; |uart_top|sel_baud_rate[1]                                          ; |uart_top|sel_baud_rate[1]                                          ; data_out0        ;
; |uart_top|sel_baud_rate[2]                                          ; |uart_top|sel_baud_rate[2]                                          ; data_out0        ;
; |uart_top|date_bus[0]                                               ; |uart_top|date_bus[0]                                               ; data_out0        ;
; |uart_top|date_bus[2]                                               ; |uart_top|date_bus[2]                                               ; data_out0        ;
; |uart_top|date_bus[4]                                               ; |uart_top|date_bus[4]                                               ; data_out0        ;
; |uart_top|date_bus[7]                                               ; |uart_top|date_bus[7]                                               ; data_out0        ;
; |uart_top|date_bus[6]                                               ; |uart_top|date_bus[6]                                               ; data_out0        ;
; |uart_top|date_bus[3]                                               ; |uart_top|date_bus[3]                                               ; data_out0        ;
; |uart_top|date_bus[5]                                               ; |uart_top|date_bus[5]                                               ; data_out0        ;
; |uart_top|date_bus[1]                                               ; |uart_top|date_bus[1]                                               ; data_out0        ;
; |uart_top|counter[3]                                                ; |uart_top|counter[3]                                                ; padio            ;
; |uart_top|bus[0]                                                    ; |uart_top|bus[0]                                                    ; padio            ;
; |uart_top|bus[1]                                                    ; |uart_top|bus[1]                                                    ; padio            ;
; |uart_top|bus[2]                                                    ; |uart_top|bus[2]                                                    ; padio            ;
; |uart_top|bus[3]                                                    ; |uart_top|bus[3]                                                    ; padio            ;
; |uart_top|bus[4]                                                    ; |uart_top|bus[4]                                                    ; padio            ;
; |uart_top|bus[5]                                                    ; |uart_top|bus[5]                                                    ; padio            ;
; |uart_top|bus[6]                                                    ; |uart_top|bus[6]                                                    ; padio            ;
; |uart_top|bus[7]                                                    ; |uart_top|bus[7]                                                    ; padio            ;
; |uart_top|error                                                     ; |uart_top|error                                                     ; padio            ;
; |uart_top|finish_s                                                  ; |uart_top|finish_s                                                  ; padio            ;
+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Dec 12 15:23:21 2006
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off uart_top -c uart_top
Warning: Ignored node in vector source file. Can't find corresponding node name "uart_emitter:uart_emitter|bus_reg[7]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "uart_emitter:uart_emitter|bus_reg[6]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "uart_emitter:uart_emitter|bus_reg[5]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "uart_emitter:uart_emitter|bus_reg[4]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "uart_emitter:uart_emitter|bus_reg[3]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "uart_emitter:uart_emitter|bus_reg[2]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "uart_emitter:uart_emitter|bus_reg[1]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "uart_emitter:uart_emitter|bus_reg[0]" in design.
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      61.40 %
Info: Number of transitions in simulation is 2009577
Info: Quartus II Simulator was successful. 0 errors, 8 warnings
    Info: Processing ended: Tue Dec 12 15:25:59 2006
    Info: Elapsed time: 00:02:40