uart_top.sim.rpt

Uart port 是一段不错的

; Complete 1/0-Value Coverage                                                                                                                                    ;
+---------------------------------------------------------------------+-----------------------------------------------------------------------+------------------+
; Node Name                                                           ; Output Port Name                                                      ; Output Port Type ;
+---------------------------------------------------------------------+-----------------------------------------------------------------------+------------------+
; |uart_top|uart_receive:uart_receiver_a|bit_counter[1]               ; |uart_top|uart_receive:uart_receiver_a|bit_counter[1]                 ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bit_counter[2]               ; |uart_top|uart_receive:uart_receiver_a|bit_counter[2]                 ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bit_counter[3]               ; |uart_top|uart_receive:uart_receiver_a|bit_counter[3]                 ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|counter[2]                   ; |uart_top|uart_receive:uart_receiver_a|counter[2]                     ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|serial                        ; |uart_top|uart_emitter:uart_emitter_a|serial                          ; data_out0        ;
; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[5]  ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[5]~57 ; cout             ;
; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[6]  ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[6]~60 ; cout             ;
; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[4]  ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[4]~63 ; cout             ;
; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~31 ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~31   ; data_out0        ;
; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[2]  ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[2]~69 ; cout             ;
; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[1]  ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[1]~72 ; cout             ;
; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[0]  ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[0]~75 ; cout             ;
; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[3]  ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp[3]~78 ; cout             ;
; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33 ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~33   ; data_out0        ;
; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34 ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~34   ; data_out0        ;
; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[2] ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[2]   ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|state.over                    ; |uart_top|uart_emitter:uart_emitter_a|state.over                      ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|state.idle                    ; |uart_top|uart_emitter:uart_emitter_a|state.idle                      ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|state                        ; |uart_top|uart_receive:uart_receiver_a|state                          ; data_out0        ;
; |uart_top|rtl~108                                                   ; |uart_top|rtl~108                                                     ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bit_counter[0]~163           ; |uart_top|uart_receive:uart_receiver_a|bit_counter[0]~163             ; data_out0        ;
; |uart_top|rtl~109                                                   ; |uart_top|rtl~109                                                     ; data_out0        ;
; |uart_top|rtl~110                                                   ; |uart_top|rtl~110                                                     ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bus[0]~15                    ; |uart_top|uart_receive:uart_receiver_a|bus[0]~15                      ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bus_reg[3]                   ; |uart_top|uart_receive:uart_receiver_a|bus_reg[3]                     ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bus_reg[4]                   ; |uart_top|uart_receive:uart_receiver_a|bus_reg[4]                     ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bus_reg[5]                   ; |uart_top|uart_receive:uart_receiver_a|bus_reg[5]                     ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bus_reg[6]                   ; |uart_top|uart_receive:uart_receiver_a|bus_reg[6]                     ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bus_reg[7]                   ; |uart_top|uart_receive:uart_receiver_a|bus_reg[7]                     ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|state.bit3                    ; |uart_top|uart_emitter:uart_emitter_a|state.bit3                      ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|state.bit1                    ; |uart_top|uart_emitter:uart_emitter_a|state.bit1                      ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|Select~135                    ; |uart_top|uart_emitter:uart_emitter_a|Select~135                      ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|state.bit8                    ; |uart_top|uart_emitter:uart_emitter_a|state.bit8                      ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|state.bit5                    ; |uart_top|uart_emitter:uart_emitter_a|state.bit5                      ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|Select~136                    ; |uart_top|uart_emitter:uart_emitter_a|Select~136                      ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|state.bit9                    ; |uart_top|uart_emitter:uart_emitter_a|state.bit9                      ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|Select~137                    ; |uart_top|uart_emitter:uart_emitter_a|Select~137                      ; data_out0        ;
; |uart_top|uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[3]    ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[3]      ; data_out0        ;
; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[1] ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[1]   ; data_out0        ;
; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[0] ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|temp0[0]   ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|state~155                    ; |uart_top|uart_receive:uart_receiver_a|state~155                      ; data_out0        ;
; |uart_top|rtl~111                                                   ; |uart_top|rtl~111                                                     ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bus_reg[0]~71                ; |uart_top|uart_receive:uart_receiver_a|bus_reg[0]~71                  ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|bus_reg[7]~0                  ; |uart_top|uart_emitter:uart_emitter_a|bus_reg[7]~0                    ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|state.bit2                    ; |uart_top|uart_emitter:uart_emitter_a|state.bit2                      ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|state.bit0                    ; |uart_top|uart_emitter:uart_emitter_a|state.bit0                      ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|state.bit7                    ; |uart_top|uart_emitter:uart_emitter_a|state.bit7                      ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|state.bit4                    ; |uart_top|uart_emitter:uart_emitter_a|state.bit4                      ; data_out0        ;
; |uart_top|uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[1]    ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[1]      ; data_out0        ;
; |uart_top|uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[0]    ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[0]      ; data_out0        ;
; |uart_top|uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[2]    ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_13:divide_13|temp[2]      ; data_out0        ;
; |uart_top|rtl~112                                                   ; |uart_top|rtl~112                                                     ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|counter~638                  ; |uart_top|uart_receive:uart_receiver_a|counter~638                    ; cascout          ;
; |uart_top|uart_receive:uart_receiver_a|counter~636                  ; |uart_top|uart_receive:uart_receiver_a|counter~636                    ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|state.bit6                    ; |uart_top|uart_emitter:uart_emitter_a|state.bit6                      ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|Select~146                    ; |uart_top|uart_emitter:uart_emitter_a|Select~146                      ; data_out0        ;
; |uart_top|rest                                                      ; |uart_top|rest                                                        ; data_out0        ;
; |uart_top|load_bus_reg                                              ; |uart_top|load_bus_reg                                                ; data_out0        ;
; |uart_top|sys_clock                                                 ; |uart_top|sys_clock                                                   ; data_out0        ;
; |uart_top|finish_F                                                  ; |uart_top|finish_F                                                    ; padio            ;
; |uart_top|bit_counter[0]                                            ; |uart_top|bit_counter[0]                                              ; padio            ;
; |uart_top|bit_counter[1]                                            ; |uart_top|bit_counter[1]                                              ; padio            ;
; |uart_top|bit_counter[2]                                            ; |uart_top|bit_counter[2]                                              ; padio            ;
; |uart_top|bit_counter[3]                                            ; |uart_top|bit_counter[3]                                              ; padio            ;
; |uart_top|counter[0]                                                ; |uart_top|counter[0]                                                  ; padio            ;
; |uart_top|counter[1]                                                ; |uart_top|counter[1]                                                  ; padio            ;
; |uart_top|counter[2]                                                ; |uart_top|counter[2]                                                  ; padio            ;
; |uart_top|serial                                                    ; |uart_top|serial                                                      ; padio            ;
; |uart_top|clock                                                     ; |uart_top|clock                                                       ; padio            ;
; |uart_top|sample_clock                                              ; |uart_top|sample_clock                                                ; padio            ;
+---------------------------------------------------------------------+-----------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                     ;
+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------+
; Node Name                                                           ; Output Port Name                                                    ; Output Port Type ;
+---------------------------------------------------------------------+---------------------------------------------------------------------+------------------+
; |uart_top|uart_receive:uart_receiver_a|bus[3]                       ; |uart_top|uart_receive:uart_receiver_a|bus[3]                       ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bus[4]                       ; |uart_top|uart_receive:uart_receiver_a|bus[4]                       ; data_out0        ;
; |uart_top|uart_receive:uart_receiver_a|bus[6]                       ; |uart_top|uart_receive:uart_receiver_a|bus[6]                       ; data_out0        ;
; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~30 ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~30 ; data_out0        ;
; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32 ; |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256|clock~32 ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|bus_reg[4]                    ; |uart_top|uart_emitter:uart_emitter_a|bus_reg[4]                    ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|bus_reg[6]                    ; |uart_top|uart_emitter:uart_emitter_a|bus_reg[6]                    ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|bus_reg[3]                    ; |uart_top|uart_emitter:uart_emitter_a|bus_reg[3]                    ; data_out0        ;
; |uart_top|uart_emitter:uart_emitter_a|Select~148                    ; |uart_top|uart_emitter:uart_emitter_a|Select~148                    ; cascout          ;
; |uart_top|sel_baud_rate[0]                                          ; |uart_top|sel_baud_rate[0]                                          ; data_out0        ;
; |uart_top|sel_baud_rate[1]                                          ; |uart_top|sel_baud_rate[1]                                          ; data_out0        ;
; |uart_top|sel_baud_rate[2]                                          ; |uart_top|sel_baud_rate[2]                                          ; data_out0        ;
; |uart_top|date_bus[0]                                               ; |uart_top|date_bus[0]                                               ; data_out0        ;
; |uart_top|date_bus[2]                                               ; |uart_top|date_bus[2]                                               ; data_out0        ;
; |uart_top|date_bus[4]                                               ; |uart_top|date_bus[4]                                               ; data_out0        ;
; |uart_top|date_bus[7]                                               ; |uart_top|date_bus[7]                                               ; data_out0        ;
; |uart_top|date_bus[6]                                               ; |uart_top|date_bus[6]                                               ; data_out0        ;