uart_top.v

Uart port 是一段不错的

module uart_top(finish_F,bit_counter,counter,bus,error,finish_s,
               serial,clock,sample_clock,sys_clock,rest,sel_baud_rate,
               load_bus_reg,date_bus);

input sys_clock,rest;
input[2:0] sel_baud_rate;
input load_bus_reg;
input [7:0] date_bus;
//////////////////////////////////
output finish_F;
output serial;
output clock,sample_clock;
///////////////////////////
//output[1:0] state_rec,next_state_rec;
output error;
output [3:0] bit_counter,counter;
output finish_s;
output [7:0] bus;
wire serial;
wire  clock,sample_clock;
 uart_clk      uart_clk_gen_a    (sel_baud_rate,sys_clock,rest,clock,sample_clock);
 uart_emitter      uart_emitter_a     (serial,finish_F,date_bus,sample_clock,rest,load_bus_reg);
 uart_receive     uart_receiver_a(bus,bit_counter,error,counter,finish_s,serial,clock,rest);
endmodule