uart_receive.map.rpt

Uart port 是一段不错的

; Ignore translate_off and translate_on Synthesis Directives                                 ; Off          ; Off           ;
; Show Parameter Settings Tables in Synthesis Report                                         ; On           ; On            ;
; Ignore Maximum Fan-Out Assignments                                                         ; Off          ; Off           ;
; Retiming Meta-Stability Register Sequence Length                                           ; 2            ; 2             ;
; HDL message level                                                                          ; Level2       ; Level2        ;
+--------------------------------------------------------------------------------------------+--------------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                       ;
+----------------------------------+-----------------+------------------------+--------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path   ;
+----------------------------------+-----------------+------------------------+--------------------------------+
; uart_receive.v                   ; yes             ; User Verilog HDL File  ; E:/verilog/uart/uart_receive.v ;
+----------------------------------+-----------------+------------------------+--------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource                        ; Usage     ;
+---------------------------------+-----------+
; Total logic elements            ; 37        ;
; Total combinational functions   ; 21        ;
;     -- Total 4-input functions  ; 15        ;
;     -- Total 3-input functions  ; 3         ;
;     -- Total 2-input functions  ; 3         ;
;     -- Total 1-input functions  ; 0         ;
;     -- Total 0-input functions  ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 26        ;
; I/O pins                        ; 21        ;
; Maximum fan-out node            ; clk       ;
; Maximum fan-out                 ; 26        ;
; Total fan-out                   ; 162       ;
; Average fan-out                 ; 2.79      ;
+---------------------------------+-----------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |uart_receive              ; 37 (37)     ; 26           ; 0           ; 21   ; 0            ; 11 (11)      ; 16 (16)           ; 10 (10)          ; 0 (0)           ; 0 (0)      ; |uart_receive       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 26    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 10    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 18    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |uart_receive ;
+----------------+-------+-----------------------------------------------------+
; Parameter Name ; Value ; Type                                                ;
+----------------+-------+-----------------------------------------------------+
; state0         ; 0     ; Binary                                              ;
; state1         ; 1     ; Binary                                              ;
+----------------+-------+-----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/verilog/uart/uart_receive.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Dec 12 00:29:58 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart_receive -c uart_receive
Info: Found 1 design units, including 1 entities, in source file uart_receive.v
    Info: Found entity 1: uart_receive
Info: Elaborating entity "uart_receive" for the top level hierarchy
Info: Power-up level of register "error~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "error~reg0" with stuck data_in port to stuck value VCC
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "error" stuck at VCC
Info: Implemented 58 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 18 output pins
    Info: Implemented 37 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Processing ended: Tue Dec 12 00:30:04 2006
    Info: Elapsed time: 00:00:07