uart_clk.tan.summary

来自「Uart port 是一段不错的」· SUMMARY 代码 · 共 107 行

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 23.591 ns
From           : divide_by_256:divide_256|temp0[2]
To             : sample_clock
From Clock     : sys_clock
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 18.277 ns
From           : sel_baud_rate[1]
To             : clock
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'sel_baud_rate[0]'
Slack          : N/A
Required Time  : None
Actual Time    : 161.32 MHz ( period = 6.199 ns )
From           : divide_by_256:divide_256|temp0[2]
To             : divide_by_256:divide_256|temp0[2]
From Clock     : sel_baud_rate[0]
To Clock       : sel_baud_rate[0]
Failed Paths   : 0

Type           : Clock Setup: 'sys_clock'
Slack          : N/A
Required Time  : None
Actual Time    : 175.72 MHz ( period = 5.691 ns )
From           : divide_by_256:divide_256|temp0[2]
To             : divide_by_256:divide_256|temp0[2]
From Clock     : sys_clock
To Clock       : sys_clock
Failed Paths   : 0

Type           : Clock Setup: 'sel_baud_rate[1]'
Slack          : N/A
Required Time  : None
Actual Time    : 211.19 MHz ( period = 4.735 ns )
From           : divide_by_256:divide_256|temp0[2]
To             : divide_by_256:divide_256|temp0[2]
From Clock     : sel_baud_rate[1]
To Clock       : sel_baud_rate[1]
Failed Paths   : 0

Type           : Clock Setup: 'sel_baud_rate[2]'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 220.99 MHz ( period = 4.525 ns )
From           : divide_by_256:divide_256|temp0[2]
To             : divide_by_256:divide_256|temp0[2]
From Clock     : sel_baud_rate[2]
To Clock       : sel_baud_rate[2]
Failed Paths   : 0

Type           : Clock Hold: 'sel_baud_rate[0]'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : divide_by_256:divide_256|temp0[0]
To             : divide_by_256:divide_256|temp0[1]
From Clock     : sel_baud_rate[0]
To Clock       : sel_baud_rate[0]
Failed Paths   : 6

Type           : Clock Hold: 'sys_clock'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : divide_by_256:divide_256|temp0[0]
To             : divide_by_256:divide_256|temp0[1]
From Clock     : sys_clock
To Clock       : sys_clock
Failed Paths   : 6

Type           : Clock Hold: 'sel_baud_rate[1]'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : divide_by_256:divide_256|temp0[0]
To             : divide_by_256:divide_256|temp0[1]
From Clock     : sel_baud_rate[1]
To Clock       : sel_baud_rate[1]
Failed Paths   : 6

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 18

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