uart_clk.map.summary

来自「Uart port 是一段不错的」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Mon Dec 11 19:41:45 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : uart_clk
Top-level Entity Name : uart_clk
Family : APEX20KE
Total logic elements : 20
Total pins : 7
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0