uart_receive.v

Uart port 是一段不错的

module uart_receive(bus,bit_counter,error,
                   counter,finish_s,serial,
                   clk,rest);
input serial;//串行总线
input clk,rest;
output error;
output finish_s;//finish_s串并转换的传送结束标志；
output[7:0] bus;
output[3:0] bit_counter,counter;
reg error;
reg[7:0] bus;
reg[7:0] bus_reg;
reg finish_s;
reg  state;
reg[3:0] bit_counter;
reg[3:0] counter;
//串－并状态机独热码编码
parameter  state0=1'b0;
parameter  state1=1'b1;
// transform of serial date to parallel date
always@(posedge clk or posedge rest)
if(rest) begin state<=state0;
               finish_s<=0;
               bit_counter<=0;
               counter<=0;
          end
else  
     case(state)
     state0: begin 
                  if(!serial) 
                      begin 
                         if(counter==3)
                            begin
                                counter<=0;
                                state<=state1;
                            end
                          else   counter<=counter+3'h1;
                      end
                    else state<=state0;
              end
     state1: begin 
                  if(counter==7) 
                       begin
                          if(bit_counter==8)
                              begin
                                   counter<=0;
                                   bit_counter<=0;
                                   if(serial)
                                      begin
                                        state<=state0;
                                        bus<=bus_reg;
                                        finish_s<=1;
                                      end
                                   else 
                                      begin
                                          error<=1;
                                          state<=state0;
                                      end 
                               end
                          else
                              begin 
                                    state<=state1;
                                    counter<=0;
                                    bit_counter<=bit_counter+3'h1;
                                    bus_reg<={serial,bus_reg[7:1]};
                              end
                         end
                   else counter<=counter+3'h1;
             end    
    default : state<=state0;
   endcase

endmodule