usrt_receive.map.eqn

Uart port 是一段不错的

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--A1L19Q is bit_counter[3]~reg0
--operation mode is normal

A1L19Q_lut_out = A1L4 & (!A1L72 # !state.receving # !A1L74);
A1L19Q = DFFE(A1L19Q_lut_out, clk, !rest, , );


--A1L17Q is bit_counter[2]~reg0
--operation mode is normal

A1L17Q_lut_out = A1L5;
A1L17Q = DFFE(A1L17Q_lut_out, clk, !rest, , );


--A1L15Q is bit_counter[1]~reg0
--operation mode is normal

A1L15Q_lut_out = A1L7;
A1L15Q = DFFE(A1L15Q_lut_out, clk, !rest, , );


--A1L13Q is bit_counter[0]~reg0
--operation mode is normal

A1L13Q_lut_out = A1L9;
A1L13Q = DFFE(A1L13Q_lut_out, clk, !rest, , );


--A1L74 is rtl~100
--operation mode is normal

A1L74 = A1L19Q & !A1L17Q & !A1L15Q & !A1L13Q;


--state.receving is state.receving
--operation mode is normal

state.receving_lut_out = A1L49 # A1L73 & state.starting & !serial;
state.receving = DFFE(state.receving_lut_out, clk, !rest, , );


--A1L84Q is sample_counter[2]~reg0
--operation mode is counter

A1L84Q_lut_out = A1L84Q $ (!A1L80);
A1L84Q_reg_input = !A1L1 & A1L84Q_lut_out;
A1L84Q = DFFE(A1L84Q_reg_input, clk, !rest, , );

--A1L83 is sample_counter[2]~37
--operation mode is counter

A1L83 = CARRY(A1L84Q & (!A1L80));


--A1L78Q is sample_counter[0]~reg0
--operation mode is counter

A1L78Q_lut_out = A1L3 $ A1L78Q;
A1L78Q_reg_input = !A1L1 & A1L78Q_lut_out;
A1L78Q = DFFE(A1L78Q_reg_input, clk, !rest, , );

--A1L77 is sample_counter[0]~40
--operation mode is counter

A1L77 = CARRY(A1L3 & A1L78Q);


--A1L81Q is sample_counter[1]~reg0
--operation mode is counter

A1L81Q_lut_out = A1L81Q $ (A1L77);
A1L81Q_reg_input = !A1L1 & A1L81Q_lut_out;
A1L81Q = DFFE(A1L81Q_reg_input, clk, !rest, , );

--A1L80 is sample_counter[1]~43
--operation mode is counter

A1L80 = CARRY(!A1L77 # !A1L81Q);


--A1L86Q is sample_counter[3]~reg0
--operation mode is normal

A1L86Q_lut_out = A1L86Q $ (A1L83);
A1L86Q_reg_input = !A1L1 & A1L86Q_lut_out;
A1L86Q = DFFE(A1L86Q_reg_input, clk, !rest, , );


--A1L72 is rtl~0
--operation mode is normal

A1L72 = A1L84Q & A1L78Q & A1L81Q & !A1L86Q;


--A1L69 is read_not_ready_out~42
--operation mode is normal

A1L69 = A1L74 & state.receving & A1L72;


--A1L70 is read_not_ready_out~43
--operation mode is normal

A1L70 = state.receving & A1L72;


--state.starting is state.starting
--operation mode is normal

state.starting_lut_out = !serial & (state.starting & !A1L73 # !state.idle);
state.starting = DFFE(state.starting_lut_out, clk, !rest, , );


--A1L73 is rtl~2
--operation mode is normal

A1L73 = A1L78Q & A1L81Q & !A1L84Q & !A1L86Q;


--A1L1 is Select~158
--operation mode is normal

A1L1 = A1L70 # state.starting & (serial # A1L73);


--A1L52Q is rcv_shiftreg[0]~reg0
--operation mode is normal

A1L52Q_lut_out = A1L54Q;
A1L52Q = DFFE(A1L52Q_lut_out, clk, !rest, , !A1L45);


--A1L54Q is rcv_shiftreg[1]~reg0
--operation mode is normal

A1L54Q_lut_out = A1L56Q;
A1L54Q = DFFE(A1L54Q_lut_out, clk, !rest, , !A1L45);


--A1L56Q is rcv_shiftreg[2]~reg0
--operation mode is normal

A1L56Q_lut_out = A1L58Q;
A1L56Q = DFFE(A1L56Q_lut_out, clk, !rest, , !A1L45);


--A1L58Q is rcv_shiftreg[3]~reg0
--operation mode is normal

A1L58Q_lut_out = A1L60Q;
A1L58Q = DFFE(A1L58Q_lut_out, clk, !rest, , !A1L45);


--A1L60Q is rcv_shiftreg[4]~reg0
--operation mode is normal

A1L60Q_lut_out = A1L62Q;
A1L60Q = DFFE(A1L60Q_lut_out, clk, !rest, , !A1L45);


--A1L62Q is rcv_shiftreg[5]~reg0
--operation mode is normal

A1L62Q_lut_out = A1L64Q;
A1L62Q = DFFE(A1L62Q_lut_out, clk, !rest, , !A1L45);


--A1L64Q is rcv_shiftreg[6]~reg0
--operation mode is normal

A1L64Q_lut_out = A1L66Q;
A1L64Q = DFFE(A1L64Q_lut_out, clk, !rest, , !A1L45);


--A1L66Q is rcv_shiftreg[7]~reg0
--operation mode is normal

A1L66Q_lut_out = serial;
A1L66Q = DFFE(A1L66Q_lut_out, clk, !rest, , !A1L45);


--A1L2 is Select~159
--operation mode is normal

A1L2 = state.starting & (!A1L73 & !serial);


--A1L3 is Select~160
--operation mode is normal

A1L3 = A1L2 # state.receving & (!A1L72);


--A1L25Q is date_bus[0]~reg0
--operation mode is normal

A1L25Q_lut_out = A1L52Q;
A1L25Q = DFFE(A1L25Q_lut_out, clk, !rest, , A1L48);


--A1L27Q is date_bus[1]~reg0
--operation mode is normal

A1L27Q_lut_out = A1L54Q;
A1L27Q = DFFE(A1L27Q_lut_out, clk, !rest, , A1L48);


--A1L29Q is date_bus[2]~reg0
--operation mode is normal

A1L29Q_lut_out = A1L56Q;
A1L29Q = DFFE(A1L29Q_lut_out, clk, !rest, , A1L48);


--A1L31Q is date_bus[3]~reg0
--operation mode is normal

A1L31Q_lut_out = A1L58Q;
A1L31Q = DFFE(A1L31Q_lut_out, clk, !rest, , A1L48);


--A1L33Q is date_bus[4]~reg0
--operation mode is normal

A1L33Q_lut_out = A1L60Q;
A1L33Q = DFFE(A1L33Q_lut_out, clk, !rest, , A1L48);


--A1L35Q is date_bus[5]~reg0
--operation mode is normal

A1L35Q_lut_out = A1L62Q;
A1L35Q = DFFE(A1L35Q_lut_out, clk, !rest, , A1L48);


--A1L37Q is date_bus[6]~reg0
--operation mode is normal

A1L37Q_lut_out = A1L64Q;
A1L37Q = DFFE(A1L37Q_lut_out, clk, !rest, , A1L48);


--A1L39Q is date_bus[7]~reg0
--operation mode is normal

A1L39Q_lut_out = A1L66Q;
A1L39Q = DFFE(A1L39Q_lut_out, clk, !rest, , A1L48);


--A1L45 is inc_bit_counter~11
--operation mode is normal

A1L45 = A1L74 # !A1L72 # !state.receving;


--A1L48 is load~29
--operation mode is normal

A1L48 = serial & A1L69 & (!read_not_ready_in);


--A1L41 is error1~26
--operation mode is normal

A1L41 = read_not_ready_in & A1L74 & state.receving & A1L72;


--A1L43 is error2~20
--operation mode is normal

A1L43 = serial # read_not_ready_in # !A1L69;


--A1L4 is add~112
--operation mode is normal

A1L4 = A1L19Q $ (A1L6);


--A1L5 is add~116
--operation mode is arithmetic

A1L5 = A1L17Q $ (!A1L8);

--A1L6 is add~118
--operation mode is arithmetic

A1L6 = CARRY(A1L17Q & (!A1L8));


--A1L7 is add~120
--operation mode is arithmetic

A1L7 = A1L15Q $ (A1L10);

--A1L8 is add~122
--operation mode is arithmetic

A1L8 = CARRY(!A1L10 # !A1L15Q);


--A1L9 is add~124
--operation mode is arithmetic

A1L9 = A1L45 $ !A1L13Q;

--A1L10 is add~126
--operation mode is arithmetic

A1L10 = CARRY(!A1L45 & A1L13Q);


--A1L49 is next_state.receving~96
--operation mode is normal

A1L49 = state.receving & (!A1L72 # !A1L74);


--state.idle is state.idle
--operation mode is normal

state.idle_lut_out = state.receving & (!A1L72 # !A1L74) # !state.receving & (!serial);
state.idle = DFFE(state.idle_lut_out, clk, !rest, , );


--serial is serial
--operation mode is input

serial = INPUT();


--read_not_ready_in is read_not_ready_in
--operation mode is input

read_not_ready_in = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--rest is rest
--operation mode is input

rest = INPUT();


--read_not_ready_out is read_not_ready_out
--operation mode is output

read_not_ready_out = OUTPUT(A1L69);


--clr_sample_counter is clr_sample_counter
--operation mode is output

clr_sample_counter = OUTPUT(A1L1);


--bit_counter[0] is bit_counter[0]
--operation mode is output

bit_counter[0] = OUTPUT(A1L13Q);


--bit_counter[1] is bit_counter[1]
--operation mode is output

bit_counter[1] = OUTPUT(A1L15Q);


--bit_counter[2] is bit_counter[2]
--operation mode is output

bit_counter[2] = OUTPUT(A1L17Q);


--bit_counter[3] is bit_counter[3]
--operation mode is output

bit_counter[3] = OUTPUT(A1L19Q);


--sample_counter[0] is sample_counter[0]
--operation mode is output

sample_counter[0] = OUTPUT(A1L78Q);


--sample_counter[1] is sample_counter[1]
--operation mode is output

sample_counter[1] = OUTPUT(A1L81Q);


--sample_counter[2] is sample_counter[2]
--operation mode is output

sample_counter[2] = OUTPUT(A1L84Q);


--sample_counter[3] is sample_counter[3]
--operation mode is output

sample_counter[3] = OUTPUT(A1L86Q);


--rcv_shiftreg[0] is rcv_shiftreg[0]
--operation mode is output

rcv_shiftreg[0] = OUTPUT(A1L52Q);


--rcv_shiftreg[1] is rcv_shiftreg[1]
--operation mode is output

rcv_shiftreg[1] = OUTPUT(A1L54Q);


--rcv_shiftreg[2] is rcv_shiftreg[2]
--operation mode is output

rcv_shiftreg[2] = OUTPUT(A1L56Q);


--rcv_shiftreg[3] is rcv_shiftreg[3]
--operation mode is output

rcv_shiftreg[3] = OUTPUT(A1L58Q);


--rcv_shiftreg[4] is rcv_shiftreg[4]
--operation mode is output

rcv_shiftreg[4] = OUTPUT(A1L60Q);


--rcv_shiftreg[5] is rcv_shiftreg[5]
--operation mode is output

rcv_shiftreg[5] = OUTPUT(A1L62Q);


--rcv_shiftreg[6] is rcv_shiftreg[6]
--operation mode is output

rcv_shiftreg[6] = OUTPUT(A1L64Q);


--rcv_shiftreg[7] is rcv_shiftreg[7]
--operation mode is output

rcv_shiftreg[7] = OUTPUT(A1L66Q);


--inc_sample_counter is inc_sample_counter
--operation mode is output

inc_sample_counter = OUTPUT(A1L3);


--clr_bit_counter is clr_bit_counter
--operation mode is output

clr_bit_counter = OUTPUT(A1L69);


--date_bus[0] is date_bus[0]
--operation mode is output

date_bus[0] = OUTPUT(A1L25Q);


--date_bus[1] is date_bus[1]
--operation mode is output

date_bus[1] = OUTPUT(A1L27Q);


--date_bus[2] is date_bus[2]
--operation mode is output

date_bus[2] = OUTPUT(A1L29Q);


--date_bus[3] is date_bus[3]
--operation mode is output

date_bus[3] = OUTPUT(A1L31Q);


--date_bus[4] is date_bus[4]
--operation mode is output

date_bus[4] = OUTPUT(A1L33Q);


--date_bus[5] is date_bus[5]
--operation mode is output

date_bus[5] = OUTPUT(A1L35Q);


--date_bus[6] is date_bus[6]
--operation mode is output

date_bus[6] = OUTPUT(A1L37Q);


--date_bus[7] is date_bus[7]
--operation mode is output

date_bus[7] = OUTPUT(A1L39Q);


--inc_bit_counter is inc_bit_counter
--operation mode is output

inc_bit_counter = OUTPUT(!A1L45);


--shift is shift
--operation mode is output

shift = OUTPUT(!A1L45);


--load is load
--operation mode is output

load = OUTPUT(A1L48);


--error1 is error1
--operation mode is output

error1 = OUTPUT(A1L41);


--error2 is error2
--operation mode is output

error2 = OUTPUT(!A1L43);