uart_top.tan.summary

来自「Uart port 是一段不错的」· SUMMARY 代码 · 共 127 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : -2.859 ns
From           : rest
To             : uart_receive:uart_receiver_a|bus_reg[7]
From Clock     : --
To Clock       : sel_baud_rate[2]
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 21.512 ns
From           : uart_emitter:uart_emitter_a|finish_F
To             : finish_F
From Clock     : sys_clock
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 12.212 ns
From           : sel_baud_rate[1]
To             : clock
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 13.522 ns
From           : rest
To             : uart_emitter:uart_emitter_a|bus_reg[7]
From Clock     : --
To Clock       : sys_clock
Failed Paths   : 0

Type           : Clock Setup: 'sys_clock'
Slack          : N/A
Required Time  : None
Actual Time    : 115.17 MHz ( period = 8.683 ns )
From           : uart_emitter:uart_emitter_a|serial
To             : uart_receive:uart_receiver_a|bus[5]
From Clock     : sys_clock
To Clock       : sys_clock
Failed Paths   : 0

Type           : Clock Setup: 'sel_baud_rate[0]'
Slack          : N/A
Required Time  : None
Actual Time    : 122.97 MHz ( period = 8.132 ns )
From           : uart_emitter:uart_emitter_a|serial
To             : uart_receive:uart_receiver_a|bus[5]
From Clock     : sel_baud_rate[0]
To Clock       : sel_baud_rate[0]
Failed Paths   : 0

Type           : Clock Setup: 'sel_baud_rate[1]'
Slack          : N/A
Required Time  : None
Actual Time    : 123.37 MHz ( period = 8.106 ns )
From           : uart_emitter:uart_emitter_a|serial
To             : uart_receive:uart_receiver_a|bus[5]
From Clock     : sel_baud_rate[1]
To Clock       : sel_baud_rate[1]
Failed Paths   : 0

Type           : Clock Setup: 'sel_baud_rate[2]'
Slack          : N/A
Required Time  : None
Actual Time    : 133.32 MHz ( period = 7.501 ns )
From           : uart_emitter:uart_emitter_a|serial
To             : uart_receive:uart_receiver_a|bus[5]
From Clock     : sel_baud_rate[2]
To Clock       : sel_baud_rate[2]
Failed Paths   : 0

Type           : Clock Hold: 'sys_clock'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : uart_emitter:uart_emitter_a|state.bit5
To             : uart_emitter:uart_emitter_a|state.bit6
From Clock     : sys_clock
To Clock       : sys_clock
Failed Paths   : 54

Type           : Clock Hold: 'sel_baud_rate[0]'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : uart_emitter:uart_emitter_a|state.bit5
To             : uart_emitter:uart_emitter_a|state.bit6
From Clock     : sel_baud_rate[0]
To Clock       : sel_baud_rate[0]
Failed Paths   : 18

Type           : Clock Hold: 'sel_baud_rate[1]'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : uart_emitter:uart_emitter_a|state.bit5
To             : uart_emitter:uart_emitter_a|state.bit6
From Clock     : sel_baud_rate[1]
To Clock       : sel_baud_rate[1]
Failed Paths   : 18

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 90

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