📄 os_cpu_a.lst
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ARM Macro Assembler Page 1
1 00000000 ;*******************************************************
*************************************************
2 00000000 ; uC/OS-II
3 00000000 ; The Real-Time
Kernel
4 00000000 ;
5 00000000 ; (c) Copyright 1992-2005,
Micrium, Weston, FL
6 00000000 ; All Rights Re
served
7 00000000 ;
8 00000000 ; Generic ARM
Port
9 00000000 ;
10 00000000 ; File : OS_CPU_A.ASM
11 00000000 ; Version : V2.00(Rev)
12 00000000 ; By : Jean J. Labrosse
13 00000000 ; Rev By : leafboy(2006.12.16-2006.12.28)
14 00000000 ;
15 00000000 ; For : ARM7 or ARM9
16 00000000 ; Mode : ARM or Thumb
17 00000000 ; Toolchain : KEIL's RV V3.03A and higher
18 00000000 ;*******************************************************
*************************************************
19 00000000
20 00000000 ; INCLUDE AT91SAM7S64.inc
21 00000000 FFFFF000
AT91C_BASE_AIC
EQU 0xFFFFF000 ;- (AIC) Base Addre
ss
22 00000000 00000100
AIC_IVR EQU 0x100 ;- IRQ Vector Regis
ter
23 00000000 00000130
AIC_EOICR
EQU 0x130 ;- End of Interrupt
Command Register
24 00000000
25 00000000 00000000
OS_TASK_SW_HOOK
EQU 0
26 00000000
27 00000000 00000001
ASM_KEILRV
EQU 1
28 00000000
29 00000000 ;--------------------------------
30 00000000 ;- ARM Core Mode and Status Bits
31 00000000 ;--------------------------------
32 00000000
33 00000000 00000010
ARM_MODE_USER
EQU 0x10
34 00000000 00000011
ARM_MODE_FIQ
EQU 0x11
35 00000000 00000012
ARM_MODE_IRQ
ARM Macro Assembler Page 2
EQU 0x12
36 00000000 00000013
ARM_MODE_SVC
EQU 0x13
37 00000000 00000017
ARM_MODE_ABORT
EQU 0x17
38 00000000 0000001B
ARM_MODE_UNDEF
EQU 0x1B
39 00000000 0000001F
ARM_MODE_SYS
EQU 0x1F
40 00000000
41 00000000 00000080
I_BIT EQU 0x80
42 00000000 00000040
F_BIT EQU 0x40
43 00000000 00000020
T_BIT EQU 0x20
44 00000000
45 00000000 EXTERN OSRunning ; External referenc
es
46 00000000 EXTERN OSPrioCur
47 00000000 EXTERN OSPrioHighRdy
48 00000000 EXTERN OSTCBCur
49 00000000 EXTERN OSTCBHighRdy
50 00000000 EXTERN OSIntNesting
51 00000000 EXTERN OSIntExit
52 00000000 EXTERN OSTaskSwHook
53 00000000
54 00000000
55 00000000 EXPORT OS_CPU_SR_Save ; Functions decl
ared in this file
56 00000000 EXPORT OS_CPU_SR_Restore
57 00000000 EXPORT OSStartHighRdy
58 00000000 EXPORT OSCtxSw
59 00000000 ;EXPORT OSIntCtxSw ; OSIntCtxSw() for OSIntExit() @ os
_core.c as null
60 00000000 EXPORT OS_CPU_IRQ_ISR
61 00000000 EXPORT OS_CPU_FIQ_ISR
62 00000000
63 00000000
64 00000000 ;*******************************************************
**************************************************
65 00000000 ; CRITICAL SECTION MET
HOD 3 FUNCTIONS
66 00000000 ;
67 00000000 ; Description: Disable/Enable interrupts by preserving t
he state of interrupts. Generally speaking you
68 00000000 ; would store the state of the interrupt di
sable flag in the local variable 'cpu_sr' and then
69 00000000 ; disable interrupts. 'cpu_sr' is allocate
d in all of uC/OS-II's functions that need to
70 00000000 ; disable interrupts. You would restore th
e interrupt disable state by copying back 'cpu_sr'
71 00000000 ; into the CPU's status register.
72 00000000 ;
73 00000000 ; Prototypes : OS_CPU_SR OS_CPU_SR_Save(void);
ARM Macro Assembler Page 3
74 00000000 ; void OS_CPU_SR_Restore(OS_CPU_S
R cpu_sr);
75 00000000 ;
76 00000000 ;
77 00000000 ; Note(s) : 1) These functions are used in general li
ke this:
78 00000000 ;
79 00000000 ; void Task (void *p_arg)
80 00000000 ; {
81 00000000 ; #if OS_CRITICAL_METHOD == 3 /
* Allocate storage for CPU status register */
82 00000000 ; OS_CPU_SR cpu_sr;
83 00000000 ; #endif
84 00000000 ;
85 00000000 ; :
86 00000000 ; :
87 00000000 ; OS_ENTER_CRITICAL(); /
* cpu_sr = OS_CPU_SaveSR(); */
88 00000000 ; :
89 00000000 ; :
90 00000000 ; OS_EXIT_CRITICAL(); /
* OS_CPU_RestoreSR(cpu_sr); */
91 00000000 ; :
92 00000000 ; :
93 00000000 ; }
94 00000000 ;
95 00000000 ; 2) OS_CPU_SaveSR() is implemented as reco
mmended by Atmel's application note:
96 00000000 ;
97 00000000 ; "Disabling Interrupts at Processor
Level"
98 00000000 ;*******************************************************
**************************************************
99 00000000 IF (ASM_KEILRV > 0)
100 00000000 PRESERVE8
101 00000000
102 00000000 AREA |.text|, CODE, READONLY
103 00000000 ARM
104 00000000 ELSE
107 ENDIF
108 00000000
109 00000000 OS_CPU_SR_Save
110 00000000 E10F0000 MRS R0,CPSR ; Set IRQ and FIQ b
its in CPSR to disa
ble all interrupts
111 00000004 E38010C0 ORR R1,R0,#(I_BIT | F_BIT)
112 00000008 E121F001 MSR CPSR_c,R1
113 0000000C E10F1000 MRS R1,CPSR ; Confirm that CPSR
contains the prope
r interrupt disable
flags
114 00000010 E20110C0 AND R1,R1,#(I_BIT | F_BIT)
115 00000014 E35100C0 CMP R1,#(I_BIT | F_BIT)
116 00000018 1AFFFFFE BNE OS_CPU_SR_Save ; Not properly d
isabled (try again)
117 0000001C E12FFF1E BX LR ; Disabled, return
the original CPSR c
ontents in R0
ARM Macro Assembler Page 4
118 00000020
119 00000020
120 00000020 OS_CPU_SR_Restore
121 00000020 E121F000 MSR CPSR_c,R0
122 00000024 E12FFF1E BX LR
123 00000028
124 00000028
125 00000028 ;*******************************************************
**************************************************
126 00000028 ; START MULTITA
SKING
127 00000028 ; void OSStartHigh
Rdy(void)
128 00000028 ;
129 00000028 ; Note(s) : 1) OSStartHighRdy() MUST:
130 00000028 ; a) Call OSTaskSwHook() then,
131 00000028 ; b) Set OSRunning to TRUE,
132 00000028 ; c) Switch to the highest priority task.
133 00000028 ;*******************************************************
**************************************************
134 00000028 IF (ASM_KEILRV > 0)
135 00000028 PRESERVE8
136 00000028
137 00000028 AREA |.text|, CODE, READONLY
138 00000028 ARM
139 00000028 ELSE
142 ENDIF
143 00000028
144 00000028 OSStartHighRdy
145 00000028
146 00000028 IF (OS_TASK_SW_HOOK >= 1)
150 ENDIF
151 00000028
152 00000028 E321F0DF MSR CPSR_c, #(I_BIT | F_BIT | ARM_M
ODE_SYS)
; Switch to SYS mod
e with IRQ and FIQ
disabled
153 0000002C
154 0000002C E59F4134 LDR R4, OS_Running
; OSRunning = TRUE
155 00000030 E3A05001 MOV R5, #1
156 00000034 E5C45000 STRB R5, [R4]
157 00000038
158 00000038 ; SWITCH TO HIGHEST PRIORITY TASK
159 00000038 E59F4130 LDR R4, OS_TCBHighRdy ; Get high
est priority task T
CB address
160 0000003C E5946000 LDR R6, [R4] ; get stack poin
ter
161 00000040
162 00000040 ;-------------------------------------------------------
--------------------------
163 00000040 ; LDR SP, [R6] ; switch to
the new stack
164 00000040
165 00000040 ; LDR R4, [SP], #4 ; pop new ta
sk's CPSR
166 00000040 ; MSR CPSR_cxsf, R4 ; has CPSR only
ARM Macro Assembler Page 5
at SYS mode
167 00000040 ; LDMFD SP!, {R0-R12,LR,PC} ; pop new ta
sk's context
168 00000040 ;-------------------------------------------------------
--------------------------
169 00000040 EA000010 B OSCtxSw2
170 00000044
171 00000044 ;*******************************************************
**************************************************
172 00000044 ; PERFORM A CONTEXT SWITCH (From
task level) - OSCtxSw()
173 00000044 ;
174 00000044 ; Note(s) : 1) OSCtxSw() is called in SYS mode with BOTH
FIQ and IRQ interrupts DISABLED
175 00000044 ;
176 00000044 ; 2) The pseudo-code for OSCtxSw() is:
177 00000044 ; a) Save the current task's context onto t
he current task's stack
178 00000044 ; b) OSTCBCur->OSTCBStkPtr = SP;
179 00000044 ; c) OSTaskSwHook();
180 00000044 ; d) OSPrioCur = OSPrioHighRdy;
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