cstartup_ice.s

更新Embest IDE for ARM 2003 软件安装后产生AT91_targets文件夹的文件内容

#------------------------------------------------------------------------------
#-         ATMEL Microcontroller Software Support  -  ROUSSET  -
#------------------------------------------------------------------------------
# The software is delivered "AS IS" without warranty or condition of any
# kind, either express, implied or statutory. This includes without
# limitation any warranty or condition with respect to merchantability or
# fitness for any particular purpose, or against the infringements of
# intellectual property rights of others.
#-----------------------------------------------------------------------------
#- File source          : cstartup_ice.s
#- Object               : Boot for simulate Final Application version to be 
#-                        loaded in SRAM. Only change as the internal RAM address
#-                        and support the Semihosting
#- Compilation flag     : SEMIHOSTING => use the semihosting facilities
#-
#- 1.0 06/04/00 JPP     : Creation
#- 1.1 18/08/00 JCZ     : Over-comment and optimize
#- 1.2 25/10/00 JPP     : Global for including
#------------------------------------------------------------------------------

#------------------------------------------------------------------------------
#- Area Definition
#-----------------
#- Must be defined as function to put first in the code as it must be mapped
#- at SRAM.
#------------------------------------------------------------------------------
#                AREA        reset, CODE, READONLY, INTERWORK

#------------------------------------------------------------------------------
#- Semihosting support
#--------------------------------
#- The C runtime library is the IO functions provided by the semihosting.
#- They are generally costly in code and can be used as the debugger mode (ICE) 
#------------------------------------------------------------------------------
#- Define "__main" to ensure that C runtime system is not linked
                .global      __main
__main:

#------------------------------------------------------------------------------
#- Define the entry point
#------------------------
#- Note on the link address and the Remap command.
#- In order to guarantee that the non position-independant code (the ARM linker 
#- armlink doesn't generate position-independant code) can work on the ARM, 
#- it must be linked at address at which it expects to run. 
#- In this startup example, we use RAM as base address. 
#------------------------------------------------------------------------------
#                ENTRY
__entry:
#------------------------------------------------------------------------------
#- Exception vectors
#--------------------
#- In the ICE function your board as run the boot code and initialize the remap
#- feature. but these code it's location independant and can be emulate the csartup_fash
#- fonctionnality.
#- These vectors are read at RAM address. in Flash mode these vectors are at 0 
#- They absolutely requires to be in relative addresssing mode in order to 
#- guarantee a valid jump. For the moment, all are just looping (what may be 
#- dangerous in a final system). If an exception occurs before remap, this 
#- would result in an infinite loop. 
#------------------------------------------------------------------------------
                B           InitReset       /* reset */
undefvec:
                B           undefvec        /* Undefined Instruction */
swivec:
                B           swivec          /* Software Interrupt */
pabtvec:
                B           pabtvec         /* Prefetch Abort */
dabtvec: 
                B           dabtvec         /* Data Abort */
rsvdvec:
                B           rsvdvec         /* reserved */
irqvec:
                B           irqvec          /* reserved */
fiqvec:
                B           fiqvec          /* reserved */

#------------------------------------------------------------------------------
#- Exception vectors ( after cstartup execution )
#------------------------------------
#- These vectors are read at RAM address after the remap command is performed in
#- the EBI. As they will be relocated at address 0x0 to be effective, a 
#- relative addressing is forbidden. The only possibility to get an absolute 
#- addressing for an ARM vector is to read a PC relative value at a defined
#- offset. It is easy to reserve the locations 0x20 to 0x3C (the 8 next
#- vectors) for storing the absolute exception handler address. 
#- The AIC vectoring access vectors are saved in the interrupt and fast 
#- interrupt ARM vectors. So, only 5 offsets are required ( reserved vector
#- offset is never used).
#- The provisory handler addresses are defined on infinite loop and can be 
#- modified at any time.
#- Note also that the reset is only accessible by a jump from the application 
#- to 0. It is an actual software reset.
#- As the 13 first location are used by the vectors, the read/write link 
#- address must be defined from 0x34 if internal data mapping is required.
#- (use for that the option -rw- base=0x34
#------------------------------------------------------------------------------
VectorTable:
                ldr         pc, [pc, #+0x18]        /* SoftReset 			*/
                ldr         pc, [pc, #+0x18]        /* UndefHandler 		*/
                ldr         pc, [pc, #+0x18]        /* SWIHandler 			*/
                ldr         pc, [pc, #+0x18]        /* PrefetchAbortHandler */
                ldr         pc, [pc, #+0x18]        /* DataAbortHandler 	*/
                nop                                 /* Reserved 			*/
                ldr         pc, [pc,#-0xF20]        /* IRQ : read the AIC 	*/
                ldr         pc, [pc,#-0xF20]        /* FIQ : read the AIC 	*/

#- There are only 5 offsets as the vectoring is used.
                .long         SoftReset
                .long         UndefHandler
                .long         SWIHandler
                .long         PrefetchAbortHandler
                .long         DataAbortHandler
#- Vectoring Execution function run at absolut addresss
SoftReset:
                b           SoftReset
UndefHandler:
                b           UndefHandler
SWIHandler:
                b           SWIHandler
PrefetchAbortHandler:
                b           PrefetchAbortHandler
DataAbortHandler:
                b           DataAbortHandler

#------------------------------------------------------------------------------
#- EBI Initialization Data
#-------------------------
#- The EBI values depend to target choice , Clock, and memories access time.
# Yous must be define these values in include file
#- The EBI User Interface Image which is copied by the boot.
#- The EBI_CSR_x are defined in the target and hardware depend.
#- That's hardware! Details in the Electrical Datasheet of the AT91 device.
#- EBI Base Address is added at the end for commodity in copy code.
#- ICE note :For ICE debug no need to set the EBI value these values already set
#- by the boot function.
#------------------------------------------------------------------------------
InitTableEBI:
            .long         EBI_CSR_0  
            .long         EBI_CSR_1  
            .long         EBI_CSR_2  
            .long         EBI_CSR_3  
            .long         EBI_CSR_4  
            .long         EBI_CSR_5  
            .long         EBI_CSR_6  
            .long         EBI_CSR_7  
            .long         0x00000001  /* REMAP command */
            .long         0x00000006  /* 6 memory regions, standard read */
PtEBIBase:
            .long         EBI_BASE    /* EBI Base Address */

#------------------------------------------------------------------------------
#- The reset handler before Remap
#--------------------------------
#- From here, the code is executed from SRAM address
#------------------------------------------------------------------------------
InitReset:

#------------------------------------------------------------------------------
#- Speed up the Boot sequence
#----------------------------
#- After reset, the number os wait states on chip select 0 is 8. All AT91 
#- Evaluation Boards fits fast flash memories, so that the number of wait 
#- states can be optimized to fast up the boot sequence.
#- ICE note :For ICE debug no need to set the EBI value these values already set
#- by the boot function.
#------------------------------------------------------------------------------
#- Load System EBI Base address and CSR0 Init Value
                ldr     r0, PtEBIBase
                ldr     r1, [pc,#-(8+.-InitTableEBI)] /* values (relative) */
    
#- Speed up code execution by disabling wait state on Chip Select 0
                str     r1, [r0]

#------------------------------------------------------------------------------
#- low level init
#----------------
# Call __low_level_init to perform initialization before initializing
# AIC and calling main. 
#----------------------------------------------------------------------

                bl      __low_level_init

#------------------------------------------------------------------------------
#- Reset the Interrupt Controller
#--------------------------------
#- Normally, the code is executed only if a reset has been actually performed.
#- So, the AIC initialization resumes at setting up the default vectors.
#------------------------------------------------------------------------------
#- Load the AIC Base Address and the default handler addresses
                add     r0, pc,#-(8+.-AicData)  /* @ where to read values (relative) */

                ldmia   r0, {r1-r4}

#- Setup the Spurious Vector
                str     r4, [r1, #AIC_SPU]      /* r4 = spurious handler */


#- ICE note : For ICE debug 
#- Perform 8 End Of Interrupt Command to make sure AIC will not lock out nIRQ
                mov         r0, #8
LoopAic0:
                str         r1, [r1, #AIC_EOICR]    /* any value written */
                subs        r0, r0, #1
                bhi         LoopAic0

#- Set up the default interrupt handler vectors
                str     r2, [r1, #AIC_SVR]      	/* SVR[0] for FIQ */
                add     r1, r1, #AIC_SVR
                mov     r0, #31                 	/* counter */
LoopAic1:
                str     r3, [r1, r0, LSL #2]    	/* SVRs for IRQs */
                subs    r0, r0, #1              	/* do not save FIQ */
                bhi     LoopAic1

                b       EndInitAic

#- Default Interrupt Handlers
AicData:
                .long     AIC_BASE                	/* AIC Base Address */
#------------------------------------------------------------------------------
#- Default Interrupt Handler
#---------------------------
#- These function are defined in the AT91 library. If you want to change this 
#- you can redifine these function in your appication code
#------------------------------------------------------------------------------

                .extern  at91_default_fiq_handler
                .extern  at91_default_irq_handler