📄 cstartup.s
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#------------------------------------------------------------------------------
#- ATMEL Microcontroller Software Support - ROUSSET -
#------------------------------------------------------------------------------
# The software is delivered "AS IS" without warranty or condition of any
# kind, either express, implied or statutory. This includes without
# limitation any warranty or condition with respect to merchantability or
# fitness for any particular purpose, or against the infringements of
# intellectual property rights of others.
#-----------------------------------------------------------------------------
#- File source : cstartup.s
#- Object : C startup choice
#-
#- 1.0 30/10/00 JPP : Creation
#- 1.1 28/06/01 JPP : Translate ADS
#- 1.2 08/01/02 PFi : March Lr test added
#------------------------------------------------------------------------------
.INCLUDE "targets/eb40a/eb40a.inc"
#------------------------------------------------------------------------------
# Angel Rom Monitor Method
#- Preprocessor Flag can be set : SEMIHOSTING
#------------------------------------------------------------------------------
.IFDEF AT91_DEBUG_ANGEL @ {
.INCLUDE "../cstartup_angel.s"
#----------------------------------------------------------------------
# Call __low_level_init to perform initialization before initializing
# AIC and calling main.
# Diasable all peripherial clock
#----------------------------------------------------------------------
__low_level_init:
mov pc,r14 @ Return
.ENDIF @ AT91_DEBUG_ANGEL }
#------------------------------------------------------------------------------
# ICE or Sram Method
#- Preprocessor Flag can be set : SEMIHOSTING
#------------------------------------------------------------------------------
.IFDEF AT91_DEBUG_ICE @ {
.INCLUDE "../cstartup_ice.s"
#----------------------------------------------------------------------
# Call __low_level_init to perform initialization before initializing
# AIC and calling main.
# Enable all peripherial clock
# The peripheral clocks are automatically enabled after a reset.
#----------------------------------------------------------------------
__low_level_init:
mvn r0,#0 @ R0<- 0xFFFFFFFF
ldr r1,=PS_BASE @ Get Power saving configuartion
str r0,[r1, #PS_PCER] @ Enable all peripherial clock
mov pc,r14 @ Return
.ENDIF @ AT91_DEBUG_ICE }
#------------------------------------------------------------------------------
# Ram run
#------------------------------------------------------------------------------
.IFDEF AT91_DEBUG_RAM @ {
.INCLUDE "../cstartup_ram.s"
#----------------------------------------------------------------------
# Call __low_level_init to perform initialization before initializing
# AIC and calling main.
# Enable all peripherial clock
# The peripheral clocks are automatically enabled after a reset.
#----------------------------------------------------------------------
__low_level_init:
mvn r0,#0 @ R0<- 0xFFFFFFFF
ldr r1,=PS_BASE @ Get Power saving configuartion
str r0,[r1, #PS_PCER] @ Enable all peripherial clock
mov pc,r14 @ Return
.ENDIF @ AT91_DEBUG_RAM }
#------------------------------------------------------------------------------
# Flash Method
#------------------------------------------------------------------------------
.IFDEF AT91_DEBUG_NONE @ {
.INCLUDE "../cstartup_flash.s"
#----------------------------------------------------------------------
# Call __low_level_init to perform initialization before initializing
# AIC and calling main.
# Diasable all peripherial clock
#----------------------------------------------------------------------
__low_level_init:
#----------------------------------------------------------------------------------------
# The March LR algorthim tests the internal SRAM memory for the AT91R40008
# This test is included only in a ROM image. In this case, it's for the boot
# software. The MARCH_LR_TEST flag is set for the boot project.
# ASM Flag to define --> SRAM_TEST_ENABLE
#----------------------------------------------------------------------------------------
.IFDEF SRAM_TEST_ENABLE @ Define only for the AT91R40008's boot code
mov r0, #0 @ r0= Internal SRAM base address
ldr r1, =0x00040000 @ r1= Internal SRAM end address
mov r2, r0 @ r2= 0x00000000 = pattern_0 for march lr test
mvn r3, r0 @ r3= 0xFFFFFFFF = pattern_1 for march lr test
mov r4, r0 @ r4= Error flag. Incremented for each error
mov r5, r0 @ r5= Dummy register for data
mov r6, r0 @ r6= Dummy register for current SRAM address value
#------------------- w0_loop0_pass1 ----------------------
w0_loop0_pass1:
cmp r6, r1
beq r0_loop1_pass1
str r2, [r6]
add r6, r6,#4
b w0_loop0_pass1
#------------------- r0_w1_loop1_pass1 -------------------
r0_loop1_pass1:
sub r6, r1,#4
sub r7, r0,#4
r0_loop_1_pass1:
cmp r6, r7
beq r1_loop2_pass1
ldr r5, [r6]
cmp r5, r2
beq w1_loop1_pass1
add r4, r4,#1
w1_loop1_pass1:
str r3, [r6]
sub r6, r6,#4
b r0_loop_1_pass1
#------------------ r1_w0_r0_w1_loop2_pass1 ----------------------
r1_loop2_pass1:
mov r6, r0
r1_loop_pass1:
cmp r6, r1
beq r1_w0_loop3_pass1
ldr r5, [r6]
cmp r5, r3
beq w0_loop2_pass1
add r4, r4,#1
w0_loop2_pass1:
str r2, [r6]
# R0
ldr r5, [r6]
cmp r5, r2
beq w1_loop2_pass1
add r4, r4,#1
w1_loop2_pass1:
str r3, [r6]
add r6, r6,#4
b r1_loop_pass1
#------------------- r1_w0_loop3_pass1 -------------------------
r1_w0_loop3_pass1:
mov r6, r0
r1_loop3_pass1:
cmp r6, r1
beq r0_w1_r1_w0_loop4_pass1
ldr r5, [r6]
cmp r5, r3
beq w0_loop3_pass1
add r4, r4,#1
w0_loop3_pass1:
str r2, [r6]
add r6, r6,#4
b r1_loop3_pass1
#------------------- r0_w1_r1_w0_loop4_pass1 -------------------------
r0_w1_r1_w0_loop4_pass1:
mov r6, r0
r0_loop4_pass1:
cmp r6, r1
beq r0_loop5_pass1
ldr r5, [r6]
cmp r5, r2
beq w1_loop4_pass1
add r4,r4,#1
w1_loop4_pass1:
str r3, [r6]
r1_loop4_pass1:
ldr r5, [r6]
cmp r5, r3
beq w0_loop4_pass1
add r4, r4,#1
w0_loop4_pass1:
str r2, [r6]
add r6, r6,#4
b r0_loop4_pass1
#------------------- r0_loop5_pass1 -------------------------
r0_loop5_pass1:
mov r6, r0
r0_loop_pass1:
cmp r6, r1
beq write_result_pass1
ldr r5, [r6]
add r6, r6,#4
cmp r5, r2
beq r0_loop_pass1
add r4, r4,#1
b r0_loop_pass1
write_result_pass1:
# Test OK
cmp r4, #0
bne test_failed_pass1
ldr r0,=0x0000BEAD
ldr r1,=0x20000
str r0,[r1]
b march_lr_end_pass1
# Test failed
test_failed_pass1:
ldr r0,=0x00000BAD
ldr r1,=0x20000
str r0,[r1]
march_lr_end_pass1:
#-------------------------------------------------------------------------------------------
# Second pass of the March LR Test with other patterns. See r2 and r3 for new pattern values
#----------------------------------------------------------------------------------------
mov r0, #0 @ r0= Internal SRAM base address
ldr r1, =0x00040000 @ r1= Internal SRAM end address
ldr r2, =0x55555555 @ r2= 0x55555555 = pattern_0 for march lr test
mvn r3, r2 @ r3= 0xAAAAAAAA = pattern_1 for march lr test
mov r4, r0 @ r4= Error flag. Incremented for each error
mov r5, r0 @ r5= Dummy register for data
mov r6, r0 @ r6= Dummy register for current SRAM address value
#------------------- w0_loop0_pass2 ----------------------
w0_loop0_pass2:
cmp r6, r1
beq r0_loop1_pass2
str r2, [r6]
add r6, r6,#4
b w0_loop0_pass2
#------------------- r0_w1_loop1_pass2 -------------------
r0_loop1_pass2:
sub r6, r1,#4
sub r7, r0,#4
r0_loop_1_pass2:
cmp r6, r7
beq r1_loop2_pass2
ldr r5, [r6]
cmp r5, r2
beq w1_loop1_pass2
add r4, r4,#1
w1_loop1_pass2:
str r3, [r6]
sub r6, r6,#4
b r0_loop_1_pass2
#------------------ r1_w0_r0_w1_loop2_pass2 ----------------------
r1_loop2_pass2:
mov r6, r0
r1_loop_pass2:
cmp r6, r1
beq r1_w0_loop3_pass2
ldr r5, [r6]
cmp r5, r3
beq w0_loop2_pass2
add r4, r4,#1
w0_loop2_pass2:
str r2, [r6]
# R0
ldr r5, [r6]
cmp r5, r2
beq w1_loop2_pass2
add r4, r4,#1
w1_loop2_pass2:
str r3, [r6]
add r6, r6,#4
b r1_loop_pass2
#------------------- r1_w0_loop3_pass2 -------------------------
r1_w0_loop3_pass2:
mov r6, r0
r1_loop3_pass2:
cmp r6, r1
beq r0_w1_r1_w0_loop4_pass2
ldr r5, [r6]
cmp r5, r3
beq w0_loop3_pass2
add r4, r4,#1
w0_loop3_pass2:
str r2, [r6]
add r6, r6,#4
b r1_loop3_pass2
#------------------- r0_w1_r1_w0_loop4_pass2 -------------------------
r0_w1_r1_w0_loop4_pass2:
mov r6, r0
r0_loop4_pass2:
cmp r6, r1
beq r0_loop5_pass2
ldr r5, [r6]
cmp r5, r2
beq w1_loop4_pass2
add r4,r4,#1
w1_loop4_pass2:
str r3, [r6]
r1_loop4_pass2:
ldr r5, [r6]
cmp r5, r3
beq w0_loop4_pass2
add r4, r4,#1
w0_loop4_pass2:
str r2, [r6]
add r6, r6,#4
b r0_loop4_pass2
#------------------- r0_loop5_pass2 -------------------------
r0_loop5_pass2:
mov r6, r0
r0_loop_pass2:
cmp r6, r1
beq write_result_pass2
ldr r5, [r6]
add r6, r6,#4
cmp r5, r2
beq r0_loop_pass2
add r4, r4,#1
b r0_loop_pass2
write_result_pass2:
# Test OK
cmp r4, #0
bne test_failed_pass2
ldr r0,=0x0000BEAD
ldr r1,=0x20004
str r0,[r1]
b march_lr_end_pass2
# Test failed
test_failed_pass2:
ldr r0,=0x00000BAD
ldr r1,=0x20004
str r0,[r1]
march_lr_end_pass2:
.ENDIF @ March LR test
#-----------------------------------------------------------
#- End of March LR 14N test -
#-----------------------------------------------------------
mov pc,r14 @ Return
.ENDIF @ AT91_DEBUG_NONE }
.END
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