arm9_deep_sleep.asm

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

;******************************************************************************
;            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
;                                                                             
;   Property of Texas Instruments 
;   For  Unrestricted  Internal  Use  Only
;   Unauthorized reproduction and/or distribution is strictly prohibited.  
;   This product is protected under copyright law and trade secret law 
;   as an unpublished work.     
; 
;   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.
;
;
;   Description : ARM9 will cut all clock to enter into deep sleep mode
;
;   Project     : Perseus
;
;   Author      : Sebastien Sabatier
; 
;******************************************************************************* 

        .state16
	.global $arm9_deep_sleep_cp15
	.global $arm9_deep_sleep_cp15_without_slfr
	.global $wait_for_interrupt
        
;
;     Input : None
;
;     Output : None
arm9_configure_deep_sleep	.macro	
	PUSH	{r0-r5, lr}
; Watchdog timer mode register:
;      Disable Watchdog functionality (by writing 0xF5 then 0xA0)
	LDR	r1, WatchdogTimerReg
	MOV	r2, #0xF5
	MOV	r3, #0xA0
	STRH	r2, [r1]
	STRH	r3, [r1]
	
; Mif Configuration Register:
;      Enable PDE bit and IMIF Power Down
	LDR	r1, MifPowerDownReg
	LDR	r2, [r1]
	MOV	r3, #0x0C
	ORR	r2, r3
	STR	r2, [r1]

; EMIF Fast Interface SDRAM Configuration Register:
;      Set "Slrf" bit
;      Disable auto-refresh mode
;      Disable Power-Down mode
;      Disable SDRAM Clock
;      Unchange others bits (SDRAM Freq, auto-refresh counter, SDRAM type. Retiming)
	LDR	r1, MifInitFastSdramReg
	LDR	r2, [r1]
	LDR	r3, MifInitFastSdramMask
	BIC	r2, r3
	LDR	r3, MifInitFastSdramMaskUpdate
	ORR	r2, r3
	STR	r2, [r1]
	
; MCU_IDLECT1 Register:
;      timer's clock is stopped when MCU enters into idle mode
;      DPLL enters into idle mode when good conditions are meet
;      Clocks INTH_CK, RHEA_CK, DMA_CK and MIFLB_CK are stopped when idle mode
;      LCD Controller's Clock is stopped when idle mode
;      MCUPER_CK is stopped when idle mode
;      OS_Timer and MCUXOR_CK are stopped when idle mode
;      Timer/Watchdog's clock is stopped when idle mode
	LDR	r3, ConfigIdleReg 
	LDR	r4, IdleRegValue 
	STRH	r4, [r3]
	
; Sets helen2 conf bit to disable RNG wakeup acknowledge
	LDR     r0, ConfigRngIdleAck
	LDR	r1, [r0]
	MOV	r2, #0x40
	BIC	r1, r2
	STR     r1, [r0]
	.endm
	

;
;     Input : None
;
;     Output : None
;
;     Limitation:	Supervisor mode need to be set before calling arm9_deep_sleep_cp15 
;(See CP15 instruction)
$arm9_deep_sleep_cp15:
	
	arm9_configure_deep_sleep
	
	ADR	r0, into_32_bis
	BX	r0
	.state32
into_32_bis
	MOV	r0, #0
	MCR	p15, #0, r0, c7, c0, #4 ; Wait-for-interrupt instruction
	ADR	r0, into_16_bis + 1
	BX	r0
	.state16
into_16_bis
	NOP
	NOP
	NOP
	NOP
	NOP
	POP	{r0-r5, pc}	; return to caller
	
;
;     Input : None
;
;     Output : None
;
;     Limitation:	Supervisor mode need to be set before calling arm9_deep_sleep_cp15_without_slfr 
;(See CP15 instruction)
$arm9_deep_sleep_cp15_without_slfr:
	PUSH	{r0-r5, lr}
; Watchdog timer mode register:
;      Disable Watchdog functionality (by writing 0xF5 then 0xA0)
	LDR	r1, WatchdogTimerReg
	MOV	r2, #0xF5
	MOV	r3, #0xA0
	STRH	r2, [r1]
	STRH	r3, [r1]
	
; Mif Configuration Register:
;      Enable PDE bit and IMIF Power Down
	LDR	r1, MifPowerDownReg
	LDR	r2, [r1]
	MOV	r3, #0x0C
	ORR	r2, r3
	STR	r2, [r1]

; EMIF Fast Interface SDRAM Configuration Register:
;      Set "Slrf" bit
;      Disable auto-refresh mode
;      Disable Power-Down mode
;      Disable SDRAM Clock
;      Unchange others bits (SDRAM Freq, auto-refresh counter, SDRAM type. Retiming)
	LDR	r1, MifInitFastSdramReg
	LDR	r2, [r1]
	LDR	r3, MifInitFastSdramMask
	BIC	r2, r3
	LDR	r3, MifInitFastSdramMaskUpdate2
	ORR	r2, r3
	STR	r2, [r1]
	
; MCU_IDLECT1 Register:
;      timer's clock is stopped when MCU enters into idle mode
;      DPLL enters into idle mode when good conditions are meet
;      Clocks INTH_CK, RHEA_CK, DMA_CK and MIFLB_CK are stopped when idle mode
;      LCD Controller's Clock is stopped when idle mode
;      MCUPER_CK is stopped when idle mode
;      OS_Timer and MCUXOR_CK are stopped when idle mode
;      Timer/Watchdog's clock is stopped when idle mode
	LDR	r3, ConfigIdleReg 
	LDR	r4, IdleRegValue 
	STRH	r4, [r3]
	
	ADR	r0, into_32_bis_2
	BX	r0
	.state32
into_32_bis_2
	MOV	r0, #0
	MCR	p15, #0, r0, c7, c0, #4 ; Wait-for-interrupt instruction
	ADR	r0, into_16_bis_2 + 1
	BX	r0
	.state16
into_16_bis_2
	NOP
	NOP
	NOP
	NOP
	NOP
	POP	{r0-r5, pc}	; return to caller


$wait_for_interrupt:	
	PUSH	{r0, lr}
	ADR	r0, into_32_bis_3
	BX	r0
	.state32
into_32_bis_3
	MOV	r0, #0
	MCR	p15, #0, r0, c7, c0, #4 ; Wait-for-interrupt instruction
	ADR	r0, into_16_bis_3 + 1
	BX	r0
	.state16
into_16_bis_3
	NOP
	NOP
	NOP
	NOP
	NOP
	POP	{r0, pc}	; return to caller



WatchdogTimerReg			.word	0xFFFEC808
MifPowerDownReg				.word	0xFFFECC0C
MifInitFastSdramReg			.word	0xFFFECC20
MifInitFastSdramMask			.word	0x04000000 ; clear PWD enable
MifInitFastSdramMaskUpdate		.word	0x08000001 ; set disable sdram clock - self refresh
MifInitFastSdramMaskUpdate2		.word	0x08000000 ; set disable sdram clock
ConfigIdleReg				.word	0xFFFECE04
ConfigRngIdleAck			.word	0xFFFE1140
IdleRegValue				.word   0x13FF
ArmIdleMask				.word   0x800

        .end