camera.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//=====================================================================
//       TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments -- For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited
// This product is protected under copyright law and trade secret law as
// an unpublished work.Created 2000,(C) Copyright 2000 Texas Instruments.
// All rights reserved.
//
//   Filename       	: camera.c
//
//   Description    	: Test Resetvalues of CAMIF  Registers by two ways:
//                       -1) non optimized access
//                       -2) optimized access
//                       Test writing in CAMIF registers by two ways:
//                       -1) non optimized access
//                       -2) optimized access
//   Purpose:           See the speed difference between these two methods
//
//   Project        	: HELEN
//
//   First creation   : Louis de Magneval ([e-mail])
//
//=====================================================================

#include "camera.h"
#include "mapping.h"
#include "errorcodes.h"

// the parameter CAMERA_IF_Base_Address has been added to switch
// between 2 different base addresses in Perseus2.5
void CAMIF_TestResetValue(UWORD32 CAMERA_IF_Base_Address)
{
  // Without the clock set, no registers can be read thus when setting
  // the clock the whole CCR register will be set and so it is unnecessary
  // to test the other bits of the CCR as they will be reseted by the
  // setting of the clock.
  

  REG32(CAMERA_IF_Base_Address + CAMIF_CCR_REG_OFFSET)=((CAMIF_CK_ENABLE)<<(CAMIF_CCR_OCPCLKEN_POS)) ;
                      


  if ( (REG32(CAMERA_IF_Base_Address + CAMIF_IR_REG_OFFSET) & (CAMIF_IR_MASK )) == (CAMIF_IR_RES_VAL) )

   RES_Set(TEST_OK);

  else RES_Set(CAMIF_IR_BAD_RESET_VALUE);


//----------------------------------------

 if ( (REG32(CAMERA_IF_Base_Address + CAMIF_MD_REG_OFFSET) & ( CAMIF_MD_MASK)) == (CAMIF_MD_RES_VAL) )

  RES_Set(TEST_OK);

 else RES_Set(CAMIF_MD_BAD_RESET_VALUE);

//-----------------------------------------


 if ( (REG32(CAMERA_IF_Base_Address + CAMIF_SR_REG_OFFSET) & ( CAMIF_SR_MASK)) == (CAMIF_SR_RES_VAL) )

  RES_Set(TEST_OK);

 else RES_Set(CAMIF_SR_BAD_RESET_VALUE);


//------------------------------------------


 if ( (REG32(CAMERA_IF_Base_Address + CAMIF_GPIO_REG_OFFSET) & (CAMIF_GPIO_MASK)) == (CAMIF_GPIO_RES_VAL) )

  RES_Set(TEST_OK);

 else RES_Set(CAMIF_GPIO_BAD_RESET_VALUE);


//------------------------------------------


 if ( (REG32(CAMERA_IF_Base_Address + CAMIF_FIFO_REG_OFFSET) & (CAMIF_FIFO_MASK)) == (CAMIF_FIFO_RES_VAL) )

   RES_Set(TEST_OK);

 else RES_Set(CAMIF_FIFO_BAD_RESET_VALUE);


}




// the parameter CAMERA_IF_Base_Address has been added to switch
// between 2 different base addresses in Persues2.5
void CAMIF_TestRegistersAccess(UWORD32 CAMERA_IF_Base_Address)
{
  REG32(CAMERA_IF_Base_Address + CAMIF_CCR_REG_OFFSET)=((CAMIF_CK_ENABLE)<<(CAMIF_CCR_OCPCLKEN_POS)) ;

//  READWRITE_ACCESS_WORK_WITH_REGISTER(CAMIF_CCR_REG,32);
//    READWRITE_ACCESS_PREPARE_OPPOSED_MASK(CAMIF_CCR_FOSCMOD,32);
//    READWRITE_ACCESS_PREPARE_OPPOSED_MASK(CAMIF_CCR_POLCLK,32);
//    READWRITE_ACCESS_PREPARE_OPPOSED_MASK(CAMIF_CCR_CAMEXCLKEN,32);
//    WRITE_MASK(CAMIF_CCR_REG,32);
//    READ_WRITE_CHECK_TEST_FIELD(CAMIF_CCR_FOSCMOD,32);
//    READ_WRITE_CHECK_TEST_FIELD(CAMIF_CCR_POLCLK,32);
//    READ_WRITE_CHECK_TEST_FIELD(CAMIF_CCR_CAMEXCLKEN,32);
//    WRITE_PREVIOUS_VALUE(CAMIF_CCR_REG,32);
//  END;

//  READWRITE_ACCESS_WORK_WITH_REGISTER(CAMIF_MD_REG,32);
//    READWRITE_ACCESS_PREPARE_OPPOSED_MASK(CAMIF_MD_CAMOSC,32);
//    READWRITE_ACCESS_PREPARE_OPPOSED_MASK(CAMIF_MD_IMGSIZE,32);
//    READWRITE_ACCESS_PREPARE_OPPOSED_MASK(CAMIF_MD_ORDERCAMD,32);
//    READWRITE_ACCESS_PREPARE_OPPOSED_MASK(CAMIF_MD_ENVUP,32);
//    READWRITE_ACCESS_PREPARE_OPPOSED_MASK(CAMIF_MD_ENVDOWN,32);
//    READWRITE_ACCESS_PREPARE_OPPOSED_MASK(CAMIF_MD_ENHUP,32);
//    READWRITE_ACCESS_PREPARE_OPPOSED_MASK(CAMIF_MD_ENHDOWN,32);
//    READWRITE_ACCESS_PREPARE_OPPOSED_MASK(CAMIF_MD_DMA,32);
//    READWRITE_ACCESS_PREPARE_OPPOSED_MASK(CAMIF_MD_THRESHOLD,32);
//    READWRITE_ACCESS_PREPARE_OPPOSED_MASK(CAMIF_MD_ENIRQ,32);
//    WRITE_MASK(CAMIF_MD_REG,32);
//    READ_WRITE_CHECK_TEST_FIELD(CAMIF_MD_CAMOSC,32);
//    READ_WRITE_CHECK_TEST_FIELD(CAMIF_MD_IMGSIZE,32);
//    READ_WRITE_CHECK_TEST_FIELD(CAMIF_MD_ORDERCAMD,32);
//    READ_WRITE_CHECK_TEST_FIELD(CAMIF_MD_ENVUP,32);
//    READ_WRITE_CHECK_TEST_FIELD(CAMIF_MD_ENVDOWN,32);
//    READ_WRITE_CHECK_TEST_FIELD(CAMIF_MD_ENHUP,32);
//    READ_WRITE_CHECK_TEST_FIELD(CAMIF_MD_ENHDOWN,32);
//    READ_WRITE_CHECK_TEST_FIELD(CAMIF_MD_DMA,32);
//    READ_WRITE_CHECK_TEST_FIELD(CAMIF_MD_THRESHOLD,32);
//    READ_WRITE_CHECK_TEST_FIELD(CAMIF_MD_ENIRQ,32);
//    WRITE_PREVIOUS_VALUE(CAMIF_MD_REG,32);
//  END;

//  MODIFY_FIELD_RESET_VALUE32(CAMIF_GPIO_REG,      CAMIF_GPIO_CAMSER);

//  MODIFY_FIELD_RESET_VALUE32(CAMIF_FIFO_REG,      CAMIF_FIFO_PC);


//  PRINT_CURRENT_ERROR_STATUS(CAMIF_TEST_REGISTER_ACCESS_SUCCEEDED);





// Test writing in CAMIF registers with optimized access


// CAMIF_GPIO_REG

 // write ~(resetvalue)

  REG32(CAMERA_IF_Base_Address + CAMIF_GPIO_REG_OFFSET)
  = (~(CAMIF_GPIO_RES_VAL) & (CAMIF_GPIO_MASK));

 // check if ~(resetvalue) writing is completed

 if ( (REG32(CAMERA_IF_Base_Address + CAMIF_GPIO_REG_OFFSET) & (CAMIF_GPIO_MASK))
      == (~(CAMIF_GPIO_RES_VAL) & (CAMIF_GPIO_MASK)) )

  RES_Set(TEST_OK);
 else
 {
  RES_Set(0xBAD);
  RES_Set(START_ARRAY_DATA);
  RES_Set((CAMERA_IF_Base_Address + CAMIF_GPIO_REG_OFFSET) >>16);
  RES_Set((CAMERA_IF_Base_Address + CAMIF_GPIO_REG_OFFSET) & 0xFFFF);
  RES_Set((REG32(CAMERA_IF_Base_Address + CAMIF_GPIO_REG_OFFSET)& (CAMIF_GPIO_MASK))  >>16);
  RES_Set((REG32(CAMERA_IF_Base_Address + CAMIF_GPIO_REG_OFFSET)& (CAMIF_GPIO_MASK)) & 0xFFFF);
  RES_Set((~(CAMIF_GPIO_RES_VAL) & ( CAMIF_GPIO_MASK)) >>16);
  RES_Set((~(CAMIF_GPIO_RES_VAL) & ( CAMIF_GPIO_MASK)) & 0xFFFF);
  RES_Set(END_ARRAY_DATA);
  }


//CAMIF_FIFO_REG

   // write ~(resetvalue)

  REG32(CAMERA_IF_Base_Address + CAMIF_FIFO_REG_OFFSET)
  = (~(CAMIF_FIFO_RES_VAL ) & (CAMIF_FIFO_MASK));

  // check if ~(resetvalue) writing is completed

 if( (REG32(CAMERA_IF_Base_Address + CAMIF_FIFO_REG_OFFSET) & (CAMIF_FIFO_MASK))
      == (~(CAMIF_FIFO_RES_VAL) & ( CAMIF_FIFO_MASK)) )

  RES_Set(TEST_OK);
 else
  {
  RES_Set(0xBAD);
  RES_Set(START_ARRAY_DATA);
  RES_Set((CAMERA_IF_Base_Address + CAMIF_FIFO_REG_OFFSET) >>16);
  RES_Set((CAMERA_IF_Base_Address + CAMIF_FIFO_REG_OFFSET) & 0xFFFF);
  RES_Set((REG32(CAMERA_IF_Base_Address + CAMIF_FIFO_REG_OFFSET)& (CAMIF_FIFO_MASK))  >>16);
  RES_Set((REG32(CAMERA_IF_Base_Address + CAMIF_FIFO_REG_OFFSET)& (CAMIF_FIFO_MASK)) & 0xFFFF);
  RES_Set((~(CAMIF_FIFO_RES_VAL) & ( CAMIF_FIFO_MASK)) >>16);
  RES_Set((~(CAMIF_FIFO_RES_VAL) & ( CAMIF_FIFO_MASK)) & 0xFFFF);
  RES_Set(END_ARRAY_DATA);
  }



 // CAMIF_MD_REG

  // write ~(resetvalue)

    REG32(CAMERA_IF_Base_Address + CAMIF_MD_REG_OFFSET)
    = (~(CAMIF_MD_RES_VAL) & (CAMIF_MD_MASK));

  // check if ~(resetvalue) writing is completed

  if ( (REG32(CAMERA_IF_Base_Address + CAMIF_MD_REG_OFFSET) & (CAMIF_MD_MASK))

     == (~(CAMIF_MD_RES_VAL) & (CAMIF_MD_MASK)) )

   RES_Set(TEST_OK);
  else
 {
  RES_Set(0xBAD);
  RES_Set(START_ARRAY_DATA);
  RES_Set((CAMERA_IF_Base_Address + CAMIF_MD_REG_OFFSET) >>16);
  RES_Set((CAMERA_IF_Base_Address + CAMIF_MD_REG_OFFSET) & 0xFFFF);
  RES_Set((REG32(CAMERA_IF_Base_Address + CAMIF_MD_REG_OFFSET)& (CAMIF_MD_MASK))  >>16);
  RES_Set((REG32(CAMERA_IF_Base_Address + CAMIF_MD_REG_OFFSET)& (CAMIF_MD_MASK)) & 0xFFFF);
  RES_Set((~(CAMIF_MD_RES_VAL) & ( CAMIF_MD_MASK)) >>16);
  RES_Set((~(CAMIF_MD_RES_VAL) & ( CAMIF_MD_MASK)) & 0xFFFF);
  RES_Set(END_ARRAY_DATA);
  }


//  PRINT_CURRENT_ERROR_STATUS(CAMIF_TEST_RESET_VALUE_SUCCEEDED);


}


//------------------------------------------------------------------
//NAME          : CAMIF_SetClockCtrlRegister
//------------------------------------------------------------------
// the parameter CAMERA_IF_Base_Address has been added to switch
// between 2 different base addresses in Persues2.5
void  CAMIF_SetClockCtrlRegister(UWORD32 ExternalClock,
                                 CAMIF_PolarityClock_T PolarityClock,
                                 CAMIF_ExternalClockEnable_T ExternalClockEnable,
                                 CAMIF_Enable_T ClockEnable,
                                 CAMIF_LCLKClockEnable_T LCLKClockEnable,
				 UWORD32 CAMERA_IF_Base_Address)
{
UWORD32 value = 0;

  // set corresponding parts of register
  value |= ExternalClock << CAMIF_CCR_FOSCMOD_POS;
  value |= PolarityClock << CAMIF_CCR_POLCLK_POS;
  value |= ExternalClockEnable << CAMIF_CCR_CAMEXCLKEN_POS;
  value |= ClockEnable << CAMIF_CCR_OCPCLKEN_POS;
  value |= LCLKClockEnable << CAMIF_CCR_LCLKEN_POS;

  // write register
  REG32(CAMERA_IF_Base_Address + CAMIF_CCR_REG_OFFSET) = value;
}


//------------------------------------------------------------------
//NAME          : CAMIF_ReadInterruptStatusRegister
//------------------------------------------------------------------
void  CAMIF_ReadInterruptStatusRegister(BOOL * const VerticalSynchRising,
                                        BOOL * const VerticalSynchFalling,
                                        BOOL * const HorizontalSynchRising,
                                        BOOL * const HorizontalSynchFalling,
                                        BOOL * const FifoFull,
                                        BOOL * const CPUIrq,
					UWORD32 CAMERA_IF_Base_Address)
{
UWORD32 value;

  // Read Interrupt Status register
  value = REG32(CAMERA_IF_Base_Address + CAMIF_IR_REG_OFFSET);

  // clear all unused bits
  value &= CAMIF_IR_REG_MASK;

  *VerticalSynchRising =  (value >> CAMIF_IR_VUP_POS) & 1;
  *VerticalSynchFalling =  (value >> CAMIF_IR_VDOWN_POS) & 1;
  *HorizontalSynchRising =  (value >> CAMIF_IR_HUP_POS) & 1;
  *HorizontalSynchFalling =  (value >> CAMIF_IR_HDOWN_POS) & 1;
  *FifoFull =  (value >> CAMIF_IR_FIFOFULL_POS) & 1;
  *CPUIrq =  (value >> CAMIF_IR_DATATRANSFER_POS) & 1;
}


//------------------------------------------------------------------
//NAME          : CAMIF_SetModeRegister
//------------------------------------------------------------------
// the parameter CAMERA_IF_Base_Address has been added to switch
// between 2 different base addresses in Persues2.5
void  CAMIF_SetModeRegister(CAMIF_SwapEnable_T SwapMode,
                            CAMIF_VerticalSyncRisingEnable_T VerticalSyncRisingEnable,
                            CAMIF_VerticalSyncFallingEnable_T VerticalSyncFallingEnable,
                            CAMIF_HorizontalSyncRisingEnable_T HorizontalSyncRisingEnable,
                            CAMIF_HorizontalSyncFallingEnable_T HorizontalSyncFallingEnable,
                            CAMIF_DMAEnable_T DMAEnable,
                            UWORD8 Threshold,
                            CAMIF_CPUIrqEnable_T CPUIrqEnable,
                            CAMIF_FifoFullEnable_T FifoFullEnable,
			    UWORD32 CAMERA_IF_Base_Address)
{
UWORD32 value = 0;

  // set corresponding parts of register
  
  value |= SwapMode << CAMIF_MD_ORDERCAMD_POS;
  value |= VerticalSyncRisingEnable << CAMIF_MD_ENVUP_POS;
  value |= VerticalSyncFallingEnable << CAMIF_MD_ENVDOWN_POS;
  value |= HorizontalSyncRisingEnable << CAMIF_MD_ENHUP_POS;
  value |= HorizontalSyncFallingEnable << CAMIF_MD_ENHDOWN_POS;
  value |= DMAEnable << CAMIF_MD_DMA_POS;
  value |= Threshold << CAMIF_MD_THRESHOLD_POS;
  value |= CPUIrqEnable << CAMIF_MD_ENIRQ_POS;
  value |= FifoFullEnable << CAMIF_MD_FIFOFULL_POS;

  // write register
  REG32(CAMERA_IF_Base_Address + CAMIF_MD_REG_OFFSET) = value;
}


//------------------------------------------------------------------
//NAME          : CAMIF_ReadStatusRegister
//------------------------------------------------------------------
void  CAMIF_ReadStatusRegister(BOOL * const VerticalSynch,
                               BOOL * const HorizontalSynch)
{
UWORD32 value;

  // Read Status register
  value = REG32(CAMIF_SR_REG);

  // clear all unused bits
  value &= CAMIF_SR_REG_MASK;

  *VerticalSynch =  (value >> CAMIF_SR_VSTATUS_POS) & 1;
  *HorizontalSynch =  (value >> CAMIF_SR_HSTATUS_POS) & 1;
}


//------------------------------------------------------------------
//NAME          : CAMIF_ReadDataRegister
//------------------------------------------------------------------
UWORD32  CAMIF_ReadDataRegister(void)
{
UWORD32 value;

  // Read Image Data register
  value = REG32(CAMIF_IMR_REG);