swatchdog.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//===============================================================================
//            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION          
//
//   Property of Texas Instruments 
//   For  Unrestricted  Internal  Use  Only
//   Unauthorized reproduction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law 
//   as an unpublished work. 
//   Created 2000, (C) Copyright 2000 Texas Instruments.  All rights reserved.
//
//   Filename             : perseus2_swatchdog.c
//   Date of Module Modification:9/25/02
//   Date of Generation :9/25/02
//
//===============================================================================
#include "global_types.h"
#include "swatchdog.h"
#include "errorcodes.h"
#include "testaccess.h"
#include "test.h"
#include "result.h"

//---------------------------------------------------------------------
// NAME        : SWATCHDOG_TestResetValue
//
// DESCRIPTION : Test the reset values of SWATCHDOG registers
//
// PARAMETERS  : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void SWDG_Test_ResetValue(void)
{
  BEGIN_RESET_MODULE();

    BEGIN_RESET_TEST(SWATCHDOG_WIDR,32);
    TEST_FIELD_RESET(SWATCHDOG_WIDR,RESERVED,32);
    TEST_FIELD_RESET(SWATCHDOG_WIDR,WD_REV,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(SWATCHDOG_WD_SYSCONFIG,32);
    TEST_FIELD_RESET(SWATCHDOG_WD_SYSCONFIG,RESERVED_0,32);
    TEST_FIELD_RESET(SWATCHDOG_WD_SYSCONFIG,EMUFREE,32);
    TEST_FIELD_RESET(SWATCHDOG_WD_SYSCONFIG,RESERVED_1,32);
    TEST_FIELD_RESET(SWATCHDOG_WD_SYSCONFIG,SOFTRESET,32);
    TEST_FIELD_RESET(SWATCHDOG_WD_SYSCONFIG,AUTOIDLE,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(SWATCHDOG_WD_SYSSTATUS,32);
    TEST_FIELD_RESET(SWATCHDOG_WD_SYSSTATUS,RESERVED_0,32);
    TEST_FIELD_RESET(SWATCHDOG_WD_SYSSTATUS,RESERVED_1,32);
    TEST_FIELD_RESET(SWATCHDOG_WD_SYSSTATUS,RESETDONE,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(SWATCHDOG_WCLR,32);
    TEST_FIELD_RESET(SWATCHDOG_WCLR,RESERVED_0,32);
    TEST_FIELD_RESET(SWATCHDOG_WCLR,PRE,32);
    TEST_FIELD_RESET(SWATCHDOG_WCLR,PTV,32);
    TEST_FIELD_RESET(SWATCHDOG_WCLR,RESERVED_1,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(SWATCHDOG_WCRR,32);
    TEST_FIELD_RESET(SWATCHDOG_WCRR,TIME_COUNTER,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(SWATCHDOG_WLDR,32);
    TEST_FIELD_RESET(SWATCHDOG_WLDR,TIME_LOAD,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(SWATCHDOG_WTGR,32);
    TEST_FIELD_RESET(SWATCHDOG_WTGR,TTGR_VALUE,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(SWATCHDOG_WWPS,32);
    TEST_FIELD_RESET(SWATCHDOG_WWPS,RESERVED,32);
    TEST_FIELD_RESET(SWATCHDOG_WWPS,W_PEND_WSPR,32);
    TEST_FIELD_RESET(SWATCHDOG_WWPS,W_PEND_WTGR,32);
    TEST_FIELD_RESET(SWATCHDOG_WWPS,W_PEND_WLDR,32);
    TEST_FIELD_RESET(SWATCHDOG_WWPS,W_PEND_WCRR,32);
    TEST_FIELD_RESET(SWATCHDOG_WWPS,W_PEND_WCLR,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(SWATCHDOG_WSPR,32);
    TEST_FIELD_RESET(SWATCHDOG_WSPR,WSPR_VALUE,32);
    END_RESET_TEST();

  END_RESET_MODULE();

}

//---------------------------------------------------------------------
// NAME        : SWDG_TestRegistersAccess
//
// DESCRIPTION : Test the access to SWATCHDOG registers
//
// PARAMETERS  : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void SWDG_TestRegistersAccess(void)
{
  BEGIN_ACCESS_MODULE();

    BEGIN_RW_TEST(SWATCHDOG_WD_SYSCONFIG,32);
    RW_PREPARE_WRITE(SWATCHDOG_WD_SYSCONFIG,RESERVED_0,32);
    RW_PREPARE_WRITE(SWATCHDOG_WD_SYSCONFIG,EMUFREE,32);
    RW_PREPARE_WRITE(SWATCHDOG_WD_SYSCONFIG,RESERVED_1,32);
    RW_PREPARE_WRITE(SWATCHDOG_WD_SYSCONFIG,SOFTRESET,32);
    RW_PREPARE_WRITE(SWATCHDOG_WD_SYSCONFIG,AUTOIDLE,32);
    RW_WRITE(SWATCHDOG_WD_SYSCONFIG);
    RW_TEST_READ(SWATCHDOG_WD_SYSCONFIG,RESERVED_0,32);
    RW_TEST_READ(SWATCHDOG_WD_SYSCONFIG,EMUFREE,32);
    RW_TEST_READ(SWATCHDOG_WD_SYSCONFIG,RESERVED_1,32);
    RW_TEST_READ(SWATCHDOG_WD_SYSCONFIG,SOFTRESET,32);
    RW_TEST_READ(SWATCHDOG_WD_SYSCONFIG,AUTOIDLE,32);
    RW_WRITE_PREVIOUS_VALUE(SWATCHDOG_WD_SYSCONFIG);
    END_RW_TEST();

    BEGIN_RW_TEST(SWATCHDOG_WCLR,32);
    RW_PREPARE_WRITE(SWATCHDOG_WCLR,RESERVED_0,32);
    RW_PREPARE_WRITE(SWATCHDOG_WCLR,PRE,32);
    RW_PREPARE_WRITE(SWATCHDOG_WCLR,PTV,32);
    RW_PREPARE_WRITE(SWATCHDOG_WCLR,RESERVED_1,32);
    RW_WRITE(SWATCHDOG_WCLR);
    RW_TEST_READ(SWATCHDOG_WCLR,RESERVED_0,32);
    RW_TEST_READ(SWATCHDOG_WCLR,PRE,32);
    RW_TEST_READ(SWATCHDOG_WCLR,PTV,32);
    RW_TEST_READ(SWATCHDOG_WCLR,RESERVED_1,32);
    RW_WRITE_PREVIOUS_VALUE(SWATCHDOG_WCLR);
    END_RW_TEST();

    BEGIN_RW_TEST(SWATCHDOG_WCRR,32);
    RW_PREPARE_WRITE(SWATCHDOG_WCRR,TIME_COUNTER,32);
    RW_WRITE(SWATCHDOG_WCRR);
    RW_TEST_READ(SWATCHDOG_WCRR,TIME_COUNTER,32);
    RW_WRITE_PREVIOUS_VALUE(SWATCHDOG_WCRR);
    END_RW_TEST();

    BEGIN_RW_TEST(SWATCHDOG_WLDR,32);
    RW_PREPARE_WRITE(SWATCHDOG_WLDR,TIME_LOAD,32);
    RW_WRITE(SWATCHDOG_WLDR);
    RW_TEST_READ(SWATCHDOG_WLDR,TIME_LOAD,32);
    RW_WRITE_PREVIOUS_VALUE(SWATCHDOG_WLDR);
    END_RW_TEST();

    BEGIN_RW_TEST(SWATCHDOG_WTGR,32);
    RW_PREPARE_WRITE(SWATCHDOG_WTGR,TTGR_VALUE,32);
    RW_WRITE(SWATCHDOG_WTGR);
    RW_TEST_READ(SWATCHDOG_WTGR,TTGR_VALUE,32);
    RW_WRITE_PREVIOUS_VALUE(SWATCHDOG_WTGR);
    END_RW_TEST();

    BEGIN_RW_TEST(SWATCHDOG_WSPR,32);
    RW_PREPARE_WRITE(SWATCHDOG_WSPR,WSPR_VALUE,32);
    RW_WRITE(SWATCHDOG_WSPR);
    RW_TEST_READ(SWATCHDOG_WSPR,WSPR_VALUE,32);
    RW_WRITE_PREVIOUS_VALUE(SWATCHDOG_WSPR);
    END_RW_TEST();

  END_ACCESS_MODULE();

}