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📄 gsm_protect.c

📁 OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器
💻 C
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    RW_WRITE_PREVIOUS_VALUE(GSM_PROTECT_PHY_START_ADD2);
    END_RW_TEST();

    BEGIN_RW_TEST(GSM_PROTECT_PHY_END_ADD2,32);
    RW_PREPARE_WRITE(GSM_PROTECT_PHY_END_ADD2,SDRAM_PHY_END_ADD2,32);
    RW_WRITE(GSM_PROTECT_PHY_END_ADD2);
    RW_TEST_READ(GSM_PROTECT_PHY_END_ADD2,SDRAM_PHY_END_ADD2,32);
    RW_WRITE_PREVIOUS_VALUE(GSM_PROTECT_PHY_END_ADD2);
    END_RW_TEST();

    BEGIN_RW_TEST(GSM_PROTECT_PHY_START_ADD3,32);
    RW_PREPARE_WRITE(GSM_PROTECT_PHY_START_ADD3,SDRAM_PHY__START_ADD3,32);
    RW_WRITE(GSM_PROTECT_PHY_START_ADD3);
    RW_TEST_READ(GSM_PROTECT_PHY_START_ADD3,SDRAM_PHY__START_ADD3,32);
    RW_WRITE_PREVIOUS_VALUE(GSM_PROTECT_PHY_START_ADD3);
    END_RW_TEST();

    BEGIN_RW_TEST(GSM_PROTECT_PHY_END_ADD3,32);
    RW_PREPARE_WRITE(GSM_PROTECT_PHY_END_ADD3,SDRAM_PHY_END_ADD3,32);
    RW_WRITE(GSM_PROTECT_PHY_END_ADD3);
    RW_TEST_READ(GSM_PROTECT_PHY_END_ADD3,SDRAM_PHY_END_ADD3,32);
    RW_WRITE_PREVIOUS_VALUE(GSM_PROTECT_PHY_END_ADD3);
    END_RW_TEST();

    BEGIN_RW_TEST(GSM_PROTECT_SDRAM_CONF_VIOLATION,32);
    //GSM_PROTECT_SDRAM_CONF_VIOLATION,EMIFF_CONF_AC is Read Only
    //GSM_PROTECT_SDRAM_CONF_VIOLATION,EMIFF_CONF_SDRAM_TYPE is Read Only
    //GSM_PROTECT_SDRAM_CONF_VIOLATION,MRS_REPLICA is Read Only
    RW_PREPARE_WRITE(GSM_PROTECT_SDRAM_CONF_VIOLATION,PROTECT_TYPE,32);
    RW_PREPARE_WRITE(GSM_PROTECT_SDRAM_CONF_VIOLATION,PROTECT_AC,32);
    RW_PREPARE_WRITE(GSM_PROTECT_SDRAM_CONF_VIOLATION,PROTECT_MRS,32);
    RW_WRITE(GSM_PROTECT_SDRAM_CONF_VIOLATION);
    //GSM_PROTECT_SDRAM_CONF_VIOLATION,EMIFF_CONF_AC is Read Only
    //GSM_PROTECT_SDRAM_CONF_VIOLATION,EMIFF_CONF_SDRAM_TYPE is Read Only
    //GSM_PROTECT_SDRAM_CONF_VIOLATION,MRS_REPLICA is Read Only
    RW_TEST_READ(GSM_PROTECT_SDRAM_CONF_VIOLATION,PROTECT_TYPE,32);
    RW_TEST_READ(GSM_PROTECT_SDRAM_CONF_VIOLATION,PROTECT_AC,32);
    RW_TEST_READ(GSM_PROTECT_SDRAM_CONF_VIOLATION,PROTECT_MRS,32);
    RW_WRITE_PREVIOUS_VALUE(GSM_PROTECT_SDRAM_CONF_VIOLATION);
    END_RW_TEST();

  END_ACCESS_MODULE();

}

void GSMP_ConfigureTcif(void)
{
  //------------------------------------------------------------
  //--  Initialize ICR and TCIF modules:                      --
  //--  Program (nCS0 in GSM) (4 MBytes)                      --
  //--    GSM_S address = 0x0000:0000 to 0x003F:FFFF          --
  //--    MPU_S Virtual Address = 0x0000:0000 to 0x003F:FFFF  --
  //--    MPU_S Physical Address = 0x0400:0000 to 0x043F:FFFF --
  //--                                                        --
  //--  Data (nCS1 in GSM) (4 MBytes)                         --
  //--    GSM_S address = 0x0100:0000 to 0x010F:FFFF          --
  //--    MPU_S Virtual Address = 0x0040:0000 to 0x007F:FFFF  --
  //--    MPU_S Physical Address = 0x1000:0000 to 0x103F:FFFF --
  //--                                                        --
  //--  Random (nCS2 in GSM) (4 MBytes)                       --
  //--    GSM_S address = 0x0180:0000 to 0x0181:FFFF          --
  //--    MPU_S Virtual Address = 0x0080:0000 to 0x00BF:FFFF  --
  //--    MPU_S Physical Address = 0x1040:0000 to 0x107F:FFFF --
  //------------------------------------------------------------
  MIFTST_EmifInitSlowCSConfigReg( MIF_Slow_nCS1,
			   MIF_MEMORY_16BIT_WIDE,
			   MIF_ASYNC_READ, // read_mode
			   0x04, // pgwst_welen
			   0x02, // write_wait_state
			   0x07, // read_wait_state
			   PIPELINE_MODE, // pipeline_flowthrough
			   MIF_NOT_RETIMED,
			   MIF_DIVIDE_BY_1,// clock divider
			   NO_FLASH_INTEL);

  // Configure Perseus Conf to enable DSP MMU clock (by bypassing logic to generate gsm_sdram_req)
  SetGroupBits(PERSEUS2_CONF_PERSEUS2_MODE2,
		 PERSEUS2_CONF_PERSEUS2_MODE2_SD_REQ_BYPASS_POS, 
		 PERSEUS2_CONF_PERSEUS2_MODE2_SD_REQ_BYPASS_NUMB, 1);
 
  // Configure ICR
  icr_set_pm_ba(0x0000);  // Program Base Address

  icr_set_dm_ba(0x0040);  // Data Base Address

  icr_set_rm_ba(0x0080);  // Random Base Address

  CLKRST_SetClockDivider(DSPMMU_DIV, CLK_DIV_BY_2);

 
  // configure size of each blocks
  icr_set_m_ctl(RESET_GSM_S, SIZE_4M, SIZE_4M, SIZE_4M, 
		NO_ICR_INTEN, ICR_INTEN); // an interrupt will be generated when 
                                         // GSM_S sets flag of ICR
}

void GSMP_ConfigureGsmProtect(UWORD32 reset_counter, UWORD8 debug_mode, UWORD8 mpu_reset, UWORD8 lock, UWORD8 gsm_reset_mode)
{
  // Enable GSM Protect Interrupt
  INTH2_InitLevel(GSM_PROTECT_INT,
                  INTH_IRQ,            
                  INTH_HIGHEST_PRIORITY,
                  INTH_FALLING_EDGE_SENSITIVE);
  INTH2_EnableOneIt(GSM_PROTECT_INT,INTH_IRQ);

  // enable PWD mode and disable SDRAM clock
  *(UWORD32*)(0xFFFECC20) |= 0x0C000000;
  *(UWORD32*)(0xFFFECC3C) |= 0x00000004;

  // Do not protect program area (mapped into flash memory)
  GSM_PROTECT_LOG_START_ADD1 = 0x00000000;
  GSM_PROTECT_LOG_END_ADD1 = 0x00000000;
  GSM_PROTECT_PHY_START_ADD1 = 0x00000000;
  GSM_PROTECT_PHY_END_ADD1 = 0x00000000;

  // Protect data area (mapped into SDRAM)
  GSM_PROTECT_LOG_START_ADD2 = 0x00400000;
  GSM_PROTECT_LOG_END_ADD2 = 0x00600000;
  GSM_PROTECT_PHY_START_ADD2 = 0x00000000;
  GSM_PROTECT_PHY_END_ADD2 = 0x00200000;

  // Do not protect Random area (mapped into SDRAM)
  GSM_PROTECT_LOG_START_ADD3 = 0x00000000;
  GSM_PROTECT_LOG_END_ADD3 = 0x00000000;
  GSM_PROTECT_PHY_START_ADD3 = 0x00000000;
  GSM_PROTECT_PHY_END_ADD3 = 0x00000000;

  SetGroupBits(GSM_PROTECT_MPU_CTL,
		GSM_PROTECT_MPU_CTL_RESET_COUNTER_POS,
		GSM_PROTECT_MPU_CTL_RESET_COUNTER_NUMB,
		reset_counter);

  SetGroupBits(GSM_PROTECT_MPU_CTL,
		GSM_PROTECT_MPU_CTL_MPU_RESET_ENABLE_POS,
		GSM_PROTECT_MPU_CTL_MPU_RESET_ENABLE_NUMB,
		mpu_reset);

  SetGroupBits(GSM_PROTECT_MPU_CTL,
		GSM_PROTECT_MPU_CTL_DEBUG_MODE_POS,
		GSM_PROTECT_MPU_CTL_DEBUG_MODE_NUMB,
		debug_mode);

  SetGroupBits(GSM_PROTECT_MPU_CTL,
		GSM_PROTECT_MPU_CTL_GSM_RESET_MODE_POS,
		GSM_PROTECT_MPU_CTL_GSM_RESET_MODE_NUMB,
		gsm_reset_mode);


  // Configure TCIF thanks to ICR
  GSMP_ConfigureTcif();

  // Configure DSP MMU
  BOOT_ConfigureDspMmuNowtl();

  // lock DSP MMU and ICR registers
  icr_set_protection();
  MMU_PROTECT_REG_DSP = 0x1; 

  // Enable GSM Protect and release GSM's reset
  *(UWORD32*)(0xFFFECC20) &= ~(0xC);                  // Disable auto-refresh when enabling GSM protect
  *(UWORD32*)(0xFFFECC84) = 2;                        // Send Manual Auto-Refresh Command
  *(UWORD32*)(0xFFFECC84) = 2;
  *(UWORD32*)(0xFFFECC84) = 2;
  *(UWORD32*)(0xFFFECC84) = 2;
  *(UWORD32*)(0xFFFECC84) = 2;
  *(UWORD32*)(0xFFFECC84) = 2;
  *(UWORD32*)(0xFFFECC84) = 2;
  *(UWORD32*)(0xFFFECC84) = 2;
  GSM_PROTECT_MPU_CTL |= (0x10000000 | lock << 29);   // Enable and lock GSM_PROTECT
  *(UWORD16*)M_CTL_REG_ADDR |= 1;                     // release GSM reset
  asm(" nop");
  asm(" nop");
  asm(" nop");
  asm(" nop");
  asm(" nop");
  asm(" nop");
  asm(" ldr r0, address0");                        // Read from SDRAM to generate a bank activate
  asm(" ldr r1, offset");
  asm(" ldr r2, [r0]");
  asm(" add r0, r1");
  asm(" ldr r2, [r0]");
  asm(" add r0, r1");
  asm(" ldr r2, [r0]");
  asm(" add r0, r1");
  asm(" ldr r2, [r0]");
  asm(" B return");
  asm("address0	.word 0x10000000");
  asm("offset	.word 0x00200000");
  asm("return:");
  asm(" nop");
  asm(" nop");

  *(UWORD32*)(0xFFFECC20) |= 0x4;                     // Re-enable auto-refresh after enabling GSM protect
  *(UWORD32*)(0xFFFECC84) = 2;                        // Send Manual Auto-Refresh Command
  *(UWORD32*)(0xFFFECC84) = 2;
  *(UWORD32*)(0xFFFECC84) = 2;
  *(UWORD32*)(0xFFFECC84) = 2;
  *(UWORD32*)(0xFFFECC84) = 2;
  *(UWORD32*)(0xFFFECC84) = 2;
  *(UWORD32*)(0xFFFECC84) = 2;
  *(UWORD32*)(0xFFFECC84) = 2;

}


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