📄 omap_32_clkrst.c
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//===============================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work.
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved.
//
// Filename : omap_32_clkrst.c
// Date of Module Modification:5/17/02
// Date of Generation :7/26/02
//
//===============================================================================
#include "global_types.h"
#include "omap_32_clkrst.h"
//#include "omap_32_clkrst_err.h"
#include "testaccess.h"
#include "test.h"
#include "errorcodes.h"
#include "result.h"
//---------------------------------------------------------------------
// NAME : CLKRST_TestResetValue
//
// DESCRIPTION : Test the reset values of CLKRST registers
//
// PARAMETERS : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void CLKRST_TestResetValue(void)
{
BEGIN_RESET_MODULE();
BEGIN_RESET_TEST(CLKRST_ARM_CKCTL,16);
// TEST_FIELD_RESET(CLKRST_ARM_CKCTL,RESERVED,16);
TEST_FIELD_RESET(CLKRST_ARM_CKCTL,ARM_INTHCK,16);
TEST_FIELD_RESET(CLKRST_ARM_CKCTL,EN_DSPCK,16);
TEST_FIELD_RESET(CLKRST_ARM_CKCTL,ARM_TIMXO,16);
TEST_FIELD_RESET(CLKRST_ARM_CKCTL,DSPMMUDIV,16);
TEST_FIELD_RESET(CLKRST_ARM_CKCTL,TCDIV,16);
TEST_FIELD_RESET(CLKRST_ARM_CKCTL,DSPDIV,16);
TEST_FIELD_RESET(CLKRST_ARM_CKCTL,ARMDIV,16);
TEST_FIELD_RESET(CLKRST_ARM_CKCTL,LCDDIV,16);
TEST_FIELD_RESET(CLKRST_ARM_CKCTL,PERDIV,16);
END_RESET_TEST();
BEGIN_RESET_TEST(CLKRST_ARM_IDLECT1,16);
// TEST_FIELD_RESET(CLKRST_ARM_IDLECT1,RESERVED,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT1,IDL_CLKOUT_ARM,16);
// TEST_FIELD_RESET(CLKRST_ARM_IDLECT1,RESERVED,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT1,WKUP_MODE,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT1,IDLTIM_ARM,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT1,IDLAPI_ARM,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT1,IDLDPLL_ARM,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT1,IDLIF_ARM,16);
// TEST_FIELD_RESET(CLKRST_ARM_IDLECT1,RESERVED,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT1,IDLLCD_ARM,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT1,IDLPER_ARM,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT1,IDLXORP_ARM,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT1,IDLWDT_ARM,16);
END_RESET_TEST();
BEGIN_RESET_TEST(CLKRST_ARM_IDLECT2,16);
// TEST_FIELD_RESET(CLKRST_ARM_IDLECT2,RESERVED,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT2,EN_CKOUT_ARM,16);
// TEST_FIELD_RESET(CLKRST_ARM_IDLECT2,RESERVED,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT2,EN_GPIOCK,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT2,DMACK_REQ,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT2,EN_TIMCK,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT2,EN_APICK,16);
// TEST_FIELD_RESET(CLKRST_ARM_IDLECT2,RESERVED,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT2,EN_LCDCK,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT2,EN_PERCK,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT2,EN_XORPCK,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT2,EN_WDTCK,16);
END_RESET_TEST();
BEGIN_RESET_TEST(CLKRST_ARM_EWUPCT,16);
// TEST_FIELD_RESET(CLKRST_ARM_EWUPCT,RESERVED,16);
TEST_FIELD_RESET(CLKRST_ARM_EWUPCT,REPWR_EN,16);
TEST_FIELD_RESET(CLKRST_ARM_EWUPCT,EXTPW,16);
END_RESET_TEST();
BEGIN_RESET_TEST(CLKRST_ARM_RSTCT1,16);
// TEST_FIELD_RESET(CLKRST_ARM_RSTCT1,RESERVED,16);
TEST_FIELD_RESET(CLKRST_ARM_RSTCT1,SW_RST,16);
TEST_FIELD_RESET(CLKRST_ARM_RSTCT1,DSP_RST,16);
TEST_FIELD_RESET(CLKRST_ARM_RSTCT1,DSP_EN,16);
TEST_FIELD_RESET(CLKRST_ARM_RSTCT1,ARM_RST,16);
END_RESET_TEST();
BEGIN_RESET_TEST(CLKRST_ARM_RSTCT2,16);
// TEST_FIELD_RESET(CLKRST_ARM_RSTCT2,RESERVED,16);
TEST_FIELD_RESET(CLKRST_ARM_RSTCT2,PER_EN,16);
END_RESET_TEST();
BEGIN_RESET_TEST(CLKRST_ARM_SYSST,16);
// TEST_FIELD_RESET(CLKRST_ARM_SYSST,RESERVED,16);
TEST_FIELD_RESET(CLKRST_ARM_SYSST,CLOCK_SELECT,16);
// TEST_FIELD_RESET(CLKRST_ARM_SYSST,RESERVED,16);
TEST_FIELD_RESET(CLKRST_ARM_SYSST,IDLE_DSP,16);
TEST_FIELD_RESET(CLKRST_ARM_SYSST,POR,16);
TEST_FIELD_RESET(CLKRST_ARM_SYSST,EXT_RST,16);
TEST_FIELD_RESET(CLKRST_ARM_SYSST,ARM_MCRST,16);
TEST_FIELD_RESET(CLKRST_ARM_SYSST,ARM_WDRST,16);
TEST_FIELD_RESET(CLKRST_ARM_SYSST,GLOB_SWRST,16);
TEST_FIELD_RESET(CLKRST_ARM_SYSST,DSP_WDRST,16);
END_RESET_TEST();
BEGIN_RESET_TEST(CLKRST_ARM_CKOUT1,16);
// TEST_FIELD_RESET(CLKRST_ARM_CKOUT1,RESERVED,16);
TEST_FIELD_RESET(CLKRST_ARM_CKOUT1,TCLKOUT,16);
TEST_FIELD_RESET(CLKRST_ARM_CKOUT1,DCLKOUT,16);
TEST_FIELD_RESET(CLKRST_ARM_CKOUT1,ACLKOUT,16);
END_RESET_TEST();
BEGIN_RESET_TEST(CLKRST_ARM_CKOUT2,16);
// TEST_FIELD_RESET(CLKRST_ARM_CKOUT2,RESERVED,16);
TEST_FIELD_RESET(CLKRST_ARM_CKOUT2,DSP_DPLL1,16);
TEST_FIELD_RESET(CLKRST_ARM_CKOUT2,ARMNDSP_RHEA,16);
END_RESET_TEST();
BEGIN_RESET_TEST(CLKRST_ARM_IDLECT3,16);
// TEST_FIELD_RESET(CLKRST_ARM_IDLECT3,RESERVED,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT3,IDLTC2_ARM,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT3,EN_TC2_CK,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT3,IDLTC1_ARM,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT3,EN_TC1_CK,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT3,IDLOCPI_ARM,16);
TEST_FIELD_RESET(CLKRST_ARM_IDLECT3,EN_OCPI_CK,16);
END_RESET_TEST();
END_RESET_MODULE();
}
//---------------------------------------------------------------------
// NAME : CLKRST_TestRegistersAccess
//
// DESCRIPTION : Test the access to CLKRST registers
//
// PARAMETERS : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void CLKRST_TestRegistersAccess(void)
{
BEGIN_ACCESS_MODULE();
BEGIN_RW_TEST(CLKRST_ARM_CKCTL,16);
// RW_PREPARE_WRITE(CLKRST_ARM_CKCTL,RESERVED,16);
RW_PREPARE_WRITE(CLKRST_ARM_CKCTL,ARM_INTHCK,16);
RW_PREPARE_WRITE(CLKRST_ARM_CKCTL,EN_DSPCK,16);
RW_PREPARE_WRITE(CLKRST_ARM_CKCTL,ARM_TIMXO,16);
RW_PREPARE_WRITE(CLKRST_ARM_CKCTL,DSPMMUDIV,16);
RW_PREPARE_WRITE(CLKRST_ARM_CKCTL,TCDIV,16);
RW_PREPARE_WRITE(CLKRST_ARM_CKCTL,DSPDIV,16);
RW_PREPARE_WRITE(CLKRST_ARM_CKCTL,ARMDIV,16);
RW_PREPARE_WRITE(CLKRST_ARM_CKCTL,LCDDIV,16);
RW_PREPARE_WRITE(CLKRST_ARM_CKCTL,PERDIV,16);
RW_WRITE(CLKRST_ARM_CKCTL);
// RW_TEST_READ(CLKRST_ARM_CKCTL,RESERVED,16);
RW_TEST_READ(CLKRST_ARM_CKCTL,ARM_INTHCK,16);
RW_TEST_READ(CLKRST_ARM_CKCTL,EN_DSPCK,16);
RW_TEST_READ(CLKRST_ARM_CKCTL,ARM_TIMXO,16);
RW_TEST_READ(CLKRST_ARM_CKCTL,DSPMMUDIV,16);
RW_TEST_READ(CLKRST_ARM_CKCTL,TCDIV,16);
RW_TEST_READ(CLKRST_ARM_CKCTL,DSPDIV,16);
RW_TEST_READ(CLKRST_ARM_CKCTL,ARMDIV,16);
RW_TEST_READ(CLKRST_ARM_CKCTL,LCDDIV,16);
RW_TEST_READ(CLKRST_ARM_CKCTL,PERDIV,16);
RW_WRITE_PREVIOUS_VALUE(CLKRST_ARM_CKCTL);
END_RW_TEST();
BEGIN_RW_TEST(CLKRST_ARM_IDLECT1,16);
// RW_PREPARE_WRITE(CLKRST_ARM_IDLECT1,RESERVED,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT1,IDL_CLKOUT_ARM,16);
// RW_PREPARE_WRITE(CLKRST_ARM_IDLECT1,RESERVED,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT1,WKUP_MODE,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT1,IDLTIM_ARM,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT1,IDLAPI_ARM,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT1,IDLDPLL_ARM,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT1,IDLIF_ARM,16);
// RW_PREPARE_WRITE(CLKRST_ARM_IDLECT1,RESERVED,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT1,IDLLCD_ARM,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT1,IDLPER_ARM,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT1,IDLXORP_ARM,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT1,IDLWDT_ARM,16);
RW_WRITE(CLKRST_ARM_IDLECT1);
// RW_TEST_READ(CLKRST_ARM_IDLECT1,RESERVED,16);
RW_TEST_READ(CLKRST_ARM_IDLECT1,IDL_CLKOUT_ARM,16);
// RW_TEST_READ(CLKRST_ARM_IDLECT1,RESERVED,16);
RW_TEST_READ(CLKRST_ARM_IDLECT1,WKUP_MODE,16);
RW_TEST_READ(CLKRST_ARM_IDLECT1,IDLTIM_ARM,16);
RW_TEST_READ(CLKRST_ARM_IDLECT1,IDLAPI_ARM,16);
RW_TEST_READ(CLKRST_ARM_IDLECT1,IDLDPLL_ARM,16);
RW_TEST_READ(CLKRST_ARM_IDLECT1,IDLIF_ARM,16);
// RW_TEST_READ(CLKRST_ARM_IDLECT1,RESERVED,16);
RW_TEST_READ(CLKRST_ARM_IDLECT1,IDLLCD_ARM,16);
RW_TEST_READ(CLKRST_ARM_IDLECT1,IDLPER_ARM,16);
RW_TEST_READ(CLKRST_ARM_IDLECT1,IDLXORP_ARM,16);
RW_TEST_READ(CLKRST_ARM_IDLECT1,IDLWDT_ARM,16);
RW_WRITE_PREVIOUS_VALUE(CLKRST_ARM_IDLECT1);
END_RW_TEST();
BEGIN_RW_TEST(CLKRST_ARM_IDLECT2,16);
// RW_PREPARE_WRITE(CLKRST_ARM_IDLECT2,RESERVED,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT2,EN_CKOUT_ARM,16);
// RW_PREPARE_WRITE(CLKRST_ARM_IDLECT2,RESERVED,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT2,EN_GPIOCK,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT2,DMACK_REQ,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT2,EN_TIMCK,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT2,EN_APICK,16);
// RW_PREPARE_WRITE(CLKRST_ARM_IDLECT2,RESERVED,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT2,EN_LCDCK,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT2,EN_PERCK,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT2,EN_XORPCK,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT2,EN_WDTCK,16);
RW_WRITE(CLKRST_ARM_IDLECT2);
// RW_TEST_READ(CLKRST_ARM_IDLECT2,RESERVED,16);
RW_TEST_READ(CLKRST_ARM_IDLECT2,EN_CKOUT_ARM,16);
// RW_TEST_READ(CLKRST_ARM_IDLECT2,RESERVED,16);
RW_TEST_READ(CLKRST_ARM_IDLECT2,EN_GPIOCK,16);
RW_TEST_READ(CLKRST_ARM_IDLECT2,DMACK_REQ,16);
RW_TEST_READ(CLKRST_ARM_IDLECT2,EN_TIMCK,16);
RW_TEST_READ(CLKRST_ARM_IDLECT2,EN_APICK,16);
// RW_TEST_READ(CLKRST_ARM_IDLECT2,RESERVED,16);
RW_TEST_READ(CLKRST_ARM_IDLECT2,EN_LCDCK,16);
RW_TEST_READ(CLKRST_ARM_IDLECT2,EN_PERCK,16);
RW_TEST_READ(CLKRST_ARM_IDLECT2,EN_XORPCK,16);
RW_TEST_READ(CLKRST_ARM_IDLECT2,EN_WDTCK,16);
RW_WRITE_PREVIOUS_VALUE(CLKRST_ARM_IDLECT2);
END_RW_TEST();
BEGIN_RW_TEST(CLKRST_ARM_EWUPCT,16);
// RW_PREPARE_WRITE(CLKRST_ARM_EWUPCT,RESERVED,16);
RW_PREPARE_WRITE(CLKRST_ARM_EWUPCT,REPWR_EN,16);
RW_PREPARE_WRITE(CLKRST_ARM_EWUPCT,EXTPW,16);
RW_WRITE(CLKRST_ARM_EWUPCT);
// RW_TEST_READ(CLKRST_ARM_EWUPCT,RESERVED,16);
RW_TEST_READ(CLKRST_ARM_EWUPCT,REPWR_EN,16);
RW_TEST_READ(CLKRST_ARM_EWUPCT,EXTPW,16);
RW_WRITE_PREVIOUS_VALUE(CLKRST_ARM_EWUPCT);
END_RW_TEST();
BEGIN_RW_TEST(CLKRST_ARM_RSTCT1,16);
// RW_PREPARE_WRITE(CLKRST_ARM_RSTCT1,RESERVED,16);
RW_PREPARE_WRITE(CLKRST_ARM_RSTCT1,SW_RST,16);
RW_PREPARE_WRITE(CLKRST_ARM_RSTCT1,DSP_RST,16);
RW_PREPARE_WRITE(CLKRST_ARM_RSTCT1,DSP_EN,16);
RW_PREPARE_WRITE(CLKRST_ARM_RSTCT1,ARM_RST,16);
RW_WRITE(CLKRST_ARM_RSTCT1);
// RW_TEST_READ(CLKRST_ARM_RSTCT1,RESERVED,16);
RW_TEST_READ(CLKRST_ARM_RSTCT1,SW_RST,16);
RW_TEST_READ(CLKRST_ARM_RSTCT1,DSP_RST,16);
RW_TEST_READ(CLKRST_ARM_RSTCT1,DSP_EN,16);
RW_TEST_READ(CLKRST_ARM_RSTCT1,ARM_RST,16);
RW_WRITE_PREVIOUS_VALUE(CLKRST_ARM_RSTCT1);
END_RW_TEST();
BEGIN_RW_TEST(CLKRST_ARM_RSTCT2,16);
// RW_PREPARE_WRITE(CLKRST_ARM_RSTCT2,RESERVED,16);
RW_PREPARE_WRITE(CLKRST_ARM_RSTCT2,PER_EN,16);
RW_WRITE(CLKRST_ARM_RSTCT2);
// RW_TEST_READ(CLKRST_ARM_RSTCT2,RESERVED,16);
RW_TEST_READ(CLKRST_ARM_RSTCT2,PER_EN,16);
RW_WRITE_PREVIOUS_VALUE(CLKRST_ARM_RSTCT2);
END_RW_TEST();
BEGIN_RW_TEST(CLKRST_ARM_SYSST,16);
// RW_PREPARE_WRITE(CLKRST_ARM_SYSST,RESERVED,16);
RW_PREPARE_WRITE(CLKRST_ARM_SYSST,CLOCK_SELECT,16);
//CLKRST_ARM_SYSST,RESERVED is Read Only
//CLKRST_ARM_SYSST,IDLE_DSP is Read Only
//CLKRST_ARM_SYSST,POR is Read Only
//CLKRST_ARM_SYSST,EXT_RST is Read Only
//CLKRST_ARM_SYSST,ARM_MCRST is Read Only
//CLKRST_ARM_SYSST,ARM_WDRST is Read Only
//CLKRST_ARM_SYSST,GLOB_SWRST is Read Only
//CLKRST_ARM_SYSST,DSP_WDRST is Read Only
RW_WRITE(CLKRST_ARM_SYSST);
// RW_TEST_READ(CLKRST_ARM_SYSST,RESERVED,16);
RW_TEST_READ(CLKRST_ARM_SYSST,CLOCK_SELECT,16);
//CLKRST_ARM_SYSST,RESERVED is Read Only
//CLKRST_ARM_SYSST,IDLE_DSP is Read Only
//CLKRST_ARM_SYSST,POR is Read Only
//CLKRST_ARM_SYSST,EXT_RST is Read Only
//CLKRST_ARM_SYSST,ARM_MCRST is Read Only
//CLKRST_ARM_SYSST,ARM_WDRST is Read Only
//CLKRST_ARM_SYSST,GLOB_SWRST is Read Only
//CLKRST_ARM_SYSST,DSP_WDRST is Read Only
RW_WRITE_PREVIOUS_VALUE(CLKRST_ARM_SYSST);
END_RW_TEST();
BEGIN_RW_TEST(CLKRST_ARM_CKOUT1,16);
// RW_PREPARE_WRITE(CLKRST_ARM_CKOUT1,RESERVED,16);
RW_PREPARE_WRITE(CLKRST_ARM_CKOUT1,TCLKOUT,16);
RW_PREPARE_WRITE(CLKRST_ARM_CKOUT1,DCLKOUT,16);
RW_PREPARE_WRITE(CLKRST_ARM_CKOUT1,ACLKOUT,16);
RW_WRITE(CLKRST_ARM_CKOUT1);
// RW_TEST_READ(CLKRST_ARM_CKOUT1,RESERVED,16);
RW_TEST_READ(CLKRST_ARM_CKOUT1,TCLKOUT,16);
RW_TEST_READ(CLKRST_ARM_CKOUT1,DCLKOUT,16);
RW_TEST_READ(CLKRST_ARM_CKOUT1,ACLKOUT,16);
RW_WRITE_PREVIOUS_VALUE(CLKRST_ARM_CKOUT1);
END_RW_TEST();
BEGIN_RW_TEST(CLKRST_ARM_CKOUT2,16);
// RW_PREPARE_WRITE(CLKRST_ARM_CKOUT2,RESERVED,16);
RW_PREPARE_WRITE(CLKRST_ARM_CKOUT2,DSP_DPLL1,16);
RW_PREPARE_WRITE(CLKRST_ARM_CKOUT2,ARMNDSP_RHEA,16);
RW_WRITE(CLKRST_ARM_CKOUT2);
// RW_TEST_READ(CLKRST_ARM_CKOUT2,RESERVED,16);
RW_TEST_READ(CLKRST_ARM_CKOUT2,DSP_DPLL1,16);
RW_TEST_READ(CLKRST_ARM_CKOUT2,ARMNDSP_RHEA,16);
RW_WRITE_PREVIOUS_VALUE(CLKRST_ARM_CKOUT2);
END_RW_TEST();
BEGIN_RW_TEST(CLKRST_ARM_IDLECT3,16);
// RW_PREPARE_WRITE(CLKRST_ARM_IDLECT3,RESERVED,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT3,IDLTC2_ARM,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT3,EN_TC2_CK,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT3,IDLTC1_ARM,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT3,EN_TC1_CK,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT3,IDLOCPI_ARM,16);
RW_PREPARE_WRITE(CLKRST_ARM_IDLECT3,EN_OCPI_CK,16);
RW_WRITE(CLKRST_ARM_IDLECT3);
// RW_TEST_READ(CLKRST_ARM_IDLECT3,RESERVED,16);
RW_TEST_READ(CLKRST_ARM_IDLECT3,IDLTC2_ARM,16);
RW_TEST_READ(CLKRST_ARM_IDLECT3,EN_TC2_CK,16);
RW_TEST_READ(CLKRST_ARM_IDLECT3,IDLTC1_ARM,16);
RW_TEST_READ(CLKRST_ARM_IDLECT3,EN_TC1_CK,16);
RW_TEST_READ(CLKRST_ARM_IDLECT3,IDLOCPI_ARM,16);
RW_TEST_READ(CLKRST_ARM_IDLECT3,EN_OCPI_CK,16);
RW_WRITE_PREVIOUS_VALUE(CLKRST_ARM_IDLECT3);
END_RW_TEST();
END_ACCESS_MODULE();
}
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