mmu.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//===============================================================================
//            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
//   Property of Texas Instruments
//   For  Unrestricted  Internal  Use  Only
//   Unauthorized reproduction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work.
//   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.
//
//   Description          : Header file for MMUs (local Bus and Modem and mmu)
//
//   Project              : OMAP3
//
//===============================================================================

#include "mmu.h"

/*
-------------------------------------------------------------------------
        MMU_IsWtlWorking                                                  -
-------------------------------------------------------------------------
*/
BOOL MMU_IsWtlWorking(MMU_NAME_t mmu_name)
{
  switch(mmu_name)
    {
    case HSAB_MMU : 
      {
	return((BOOL)(TestBit(WALKING_ST_REG_HSAB,WTL_WORKING_MASK)));
      }
    case LB_MMU : 
      {
	return((BOOL)(TestBit(WALKING_ST_REG_LOCAL_BUS,WTL_WORKING_MASK)));
      }
    case DSP_MMU : 
      {
	return((BOOL)(TestBit(WALKING_ST_REG_DSP,WTL_WORKING_MASK)));
      }
    default : return((BOOL)FALSE);
    }
}


/*
-------------------------------------------------------------------------
        MMU_ReadFaultAddress                                              -
-------------------------------------------------------------------------
*/
UWORD32 MMU_ReadFaultAddress(MMU_NAME_t mmu_name)
{
  switch(mmu_name)
    {
    case HSAB_MMU : 
      {
	return(((FAULT_AD_L_REG_HSAB) & 0xFFFF) | 
	       ((FAULT_AD_H_REG_HSAB) << 16));
      }
    case LB_MMU : 
      {
       return(((FAULT_AD_L_REG_LOCAL_BUS) & 0xFFFF) | 
	      ((FAULT_AD_H_REG_LOCAL_BUS) << 16));
      }
    case DSP_MMU : 
      {
	return(((FAULT_AD_L_REG_DSP) & 0xFFFF) | 
	       ((FAULT_AD_H_REG_DSP) << 16));
      }
    default : return(0);
    }
}

/*
-------------------------------------------------------------------------
        MMU_ReadFaultStatus                                               -
-------------------------------------------------------------------------
*/
FAULT_STATUS_t MMU_ReadFaultStatus(MMU_NAME_t mmu_name)
{
  switch(mmu_name)
    {
    case HSAB_MMU : 
      {
	return((FAULT_STATUS_t)(FAULT_ST_REG_HSAB & 0xFFFF));
      }
    case LB_MMU : 
      {
	return((FAULT_STATUS_t)(FAULT_ST_REG_LOCAL_BUS & 0xFFFF));
      }
    case DSP_MMU : 
      {
	return((FAULT_STATUS_t)(FAULT_ST_REG_DSP & 0xFFFF));
      }
    default : return((FAULT_STATUS_t)0);
    }
}

/*
-------------------------------------------------------------------------
        MMU_ReadTtb                                                        -
-------------------------------------------------------------------------
*/
UWORD32 MMU_ReadTtb(MMU_NAME_t mmu_name)
{
  switch(mmu_name)
    {
    case HSAB_MMU : 
      {
	return(((TTB_L_REG_HSAB) & 0xFFFF) | 
	       ((TTB_H_REG_HSAB) << 16));
      }
    case LB_MMU : 
      {
	return(((TTB_L_REG_LOCAL_BUS) & 0xFFFF) | 
	       ((TTB_H_REG_LOCAL_BUS) << 16));
      }
    case DSP_MMU : 
      {
	return(((TTB_L_REG_DSP) & 0xFFFF) | 
	       ((TTB_H_REG_DSP) << 16));
      }
    default : return(0);
    }
}

/*
-------------------------------------------------------------------------
        MMU_ReadLockCounter                                               -
-------------------------------------------------------------------------
*/
UWORD16 MMU_ReadLockCounter(MMU_NAME_t mmu_name)
{
  switch(mmu_name)
    {
    case HSAB_MMU : 
      {
	return((LOCK_REG_HSAB & 0xFFFF));
      }
    case LB_MMU : 
      {
	return((LOCK_REG_LOCAL_BUS & 0xFFFF));
      }
    case DSP_MMU : 
      {
	return((LOCK_REG_DSP & 0xFFFF));
      }
    default : return(0);
    }
}

/*
-------------------------------------------------------------------------
        MMU_ReadBaseValue                                                 -
-------------------------------------------------------------------------
*/
UWORD8 MMU_ReadBaseValue(MMU_NAME_t mmu_name)
{
  switch(mmu_name)
    {
    case HSAB_MMU : 
      {
	return(((LOCK_REG_HSAB & 0xFC00) >> 10));
      }
    case LB_MMU : 
      {
	return(((LOCK_REG_LOCAL_BUS & 0xFC00) >> 10));
      }
    case DSP_MMU : 
      {
	return(((LOCK_REG_DSP & 0xFC00) >> 10));
      }
    default : return(0);
    }
}

/*
-------------------------------------------------------------------------
        MMU_ReadCurrentVictim                                             -
-------------------------------------------------------------------------
*/
UWORD8 MMU_ReadCurrentVictim(MMU_NAME_t mmu_name)
{
  switch(mmu_name)
    {
    case HSAB_MMU : 
      {
	return(((LOCK_REG_HSAB & 0x03F0) >> 4));
      }
    case LB_MMU : 
      {
	return(((LOCK_REG_LOCAL_BUS & 0x03F0) >> 4));
      }
    case DSP_MMU : 
      {
	return(((LOCK_REG_DSP & 0x03F0) >> 4));
      }
    default : return(0);
    }
}

/*
-------------------------------------------------------------------------
        MMU_ReadCamEntry                                                  -
-------------------------------------------------------------------------
*/
UWORD32 MMU_ReadCamEntry(MMU_NAME_t mmu_name)
{
  switch(mmu_name)
    {
    case HSAB_MMU : 
      {
	return(((READ_CAM_L_REG_HSAB & 0xFFFF) |
		(READ_CAM_H_REG_HSAB << 16)));
      }
    case LB_MMU : 
      {
	return(((READ_CAM_L_REG_LOCAL_BUS & 0xFFFF) |
		(READ_CAM_H_REG_LOCAL_BUS << 16)));
      }
    case DSP_MMU : 
      {
	return(((READ_CAM_L_REG_DSP & 0xFFFF) |
		(READ_CAM_H_REG_DSP << 16)));
      }
    default : return(0);
    }
}

/*
-------------------------------------------------------------------------
        MMU_IsCamEntryValid                                              -
-------------------------------------------------------------------------
*/
BOOL MMU_IsCamEntryValid(MMU_NAME_t mmu_name)
{
  switch(mmu_name)
    {
    case HSAB_MMU : 
      {
	return((BOOL)((CAM_L_REG_HSAB & 4) >> 2));
      }
    case LB_MMU : 
      {
	return((BOOL)((CAM_L_REG_LOCAL_BUS & 4) >> 2));
      }
    case DSP_MMU : 
      {
	return((BOOL)((CAM_L_REG_DSP & 4) >> 2));
      }
    default : return(False);
    }
}

/*
-------------------------------------------------------------------------
        MMU_ReadRamEntry                                                  -
-------------------------------------------------------------------------
*/
UWORD32 MMU_ReadRamEntry(MMU_NAME_t mmu_name)
{
  switch(mmu_name)
    {
    case HSAB_MMU : 
      {
	return(((READ_RAM_L_REG_HSAB & 0xFFFF) |
		(READ_RAM_H_REG_HSAB << 16)));
      }
    case LB_MMU : 
      {
	return(((READ_RAM_L_REG_LOCAL_BUS & 0xFFFF) |
		(READ_RAM_H_REG_LOCAL_BUS << 16)));
      }
    case DSP_MMU : 
      {
	return(((READ_RAM_L_REG_DSP & 0xFFFF) |
		(READ_RAM_H_REG_DSP << 16)));
      }
    default : return(0);
    }
}

/*
-------------------------------------------------------------------------
        MMU_WriteTlbEntry                                                 -
-------------------------------------------------------------------------
*/
void MMU_WriteTlbEntry(MMU_NAME_t  mmu_name,
		     UWORD32     physical_address,
		     UWORD32     virtual_address,
		     SLST_t      slst_bit,
		     AP_t        ap_bits,
		     UWORD8      locked_base_value, // between 0 and 31
		     UWORD8      current_entry,     // between base_value and 31
		     PRESERVED_t p_bit)
{
UWORD16 VA_tag_I2, VA_tag_I1;
  VA_tag_I1 = ((virtual_address & 0xFFF00000) >> 20);
  VA_tag_I2 = ((virtual_address & 0x000FFC00) >> 10);

  // Write CAM msb and lsb into CAM_REG_H and CAM_REG_L registers
  Set_CAM_Entry(mmu_name, slst_bit, p_bit, VA_tag_I2, VA_tag_I1);

  // Write RAM msb and lsb into RAM_REG_H and RAM_REG_L registers
  Set_RAM_Entry(mmu_name, physical_address, ap_bits);

  // Update lock counter register
  Update_Lock_Counter(mmu_name, current_entry, locked_base_value);

  // write 1 into LD_TLB_REG register
  Load_Entry_In_TLB(mmu_name);

}

/*
-------------------------------------------------------------------------
        READ_TLB_Entry                                                 -
-------------------------------------------------------------------------
*/
void MMU_ReadTlbEntry(MMU_NAME_t  mmu_name,
		     UWORD8      locked_base_value, // between 0 and 31
		     UWORD8      current_entry)     // between base_value and 31
		     
{


  // Update lock counter register
  Update_Lock_Counter(mmu_name, current_entry, locked_base_value);

  // write 2 into LD_TLB_REG register
  Read_Entry_In_TLB(mmu_name);

 // The rhea read_cam_h, read_cam_l, read_ram_h, read_ram_l registers are
 // now updated with the data that is stored by the address of lock counter


}


UWORD16 MMU_CheckRamEntry(MMU_NAME_t  mmu_name,
		     	UWORD32     physical_address,
		     	AP_t        ap_bits)
{
#define ERROR_RAM_H_REG	0x4
#define ERROR_RAM_L_REG	0x8

UWORD16 error_code = 0;

switch(mmu_name) 
    { 
    case HSAB_MMU : 
      { 
       if (RAM_H_REG_HSAB != (physical_address >> 16))
		 		error_code = ERROR_RAM_H_REG;
       if (RAM_L_REG_HSAB != ((ap_bits << 8) | (physical_address & 0x0000FC00)))
		 		error_code += ERROR_RAM_L_REG;
       break; 
      } 
    case LB_MMU : 
      { 
       if (RAM_H_REG_LOCAL_BUS != (physical_address >> 16))
		 		error_code = ERROR_RAM_H_REG;
       if (RAM_L_REG_LOCAL_BUS != ((ap_bits << 8) | (physical_address & 0x0000FC00)))
		 		error_code += ERROR_RAM_L_REG;
       break; 
      } 
    case DSP_MMU : 
      { 
       if (RAM_H_REG_DSP != (physical_address >> 16))
		 		error_code = ERROR_RAM_H_REG;
       if (RAM_L_REG_DSP != ((ap_bits << 8) | (physical_address & 0x0000FC00)))
		 		error_code += ERROR_RAM_L_REG;
       break; 
      } 
	}
return(error_code);
}

/*
-------------------------------------------------------------------------
        MMU_Section                                                     -
-------------------------------------------------------------------------
*/
void MMU_Section(MMU_NAME_t mmu_name, 
		 UWORD32 PA,
		 UWORD32 VA,
		 UWORD32 TTB,
		 AP_t AP_bits)
{
int add_D1, val_D1;

 if (mmu_name == HSAB_MMU)
   add_D1 = ((TTB & 0xFFFFF000) | (((VA >> 20) << 2) & 0xFFF));
 else if (mmu_name == LB_MMU)
   add_D1 = ((TTB & 0xFFFFFC00) | (((VA >> 20) << 2) & 0x3FF));
 else
   add_D1 = ((TTB & 0xFFFFF000) | (((VA >> 20) << 2) & 0xFFF));
 val_D1 = ((PA & 0xFFF00000) | (AP_bits << 10) | 2);

 *(UWORD32*)add_D1 = val_D1;
}

/*
-------------------------------------------------------------------------
        MMU_CoarseLargePage                                             -
-------------------------------------------------------------------------
*/
void MMU_CoarseLargePage(MMU_NAME_t mmu_name,
			 UWORD32 PA,
			 UWORD32 VA,
			 UWORD32 TTB,
			 UWORD32 page_table_base,
			 AP_t AP_bits)
{ 
UWORD32 add_D1, val_D1, add_D2, val_D2, i;

 if (mmu_name == HSAB_MMU)
   add_D1 = ((TTB & 0xFFFFF000) | (((VA >> 20) << 2) & 0xFFF));
 else if (mmu_name == LB_MMU)
   add_D1 = ((TTB & 0xFFFFFC00) | (((VA >> 20) << 2) & 0x3FF));
 else
   add_D1 = ((TTB & 0xFFFFF000) | (((VA >> 20) << 2) & 0xFFF));
 val_D1 = ((page_table_base & 0xFFFFFC00) | 1);
 add_D2 = ((page_table_base & 0xFFFFFC00) | ((VA & 0x000FF000) >> 10));
 val_D2 = ((PA & 0xFFFF0000) | (AP_bits << 4) | 1);

 *(UWORD32*)add_D1 = val_D1;

 for (i = 0; i < 256; i++)
   {
      *(UWORD32*)(add_D2 + 4*i) = val_D2;
   }
}

/*
-------------------------------------------------------------------------
        MMU_FineLargePage                                               -
-------------------------------------------------------------------------