📄 api.c
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//===============================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work.
// Created 1999, (C) Copyright 1999 Texas Instruments. All rights reserved.
//
// Description : ARM Port Interface
//
// Project : OMAP3
//
//===============================================================================
#include "api.h"
#include "dsp_mb.h"
#include "dsp_gpio.h"
#include "dsp_clkm.h"
#include "test.h"
//-----------------------------------------------------------------------
// API_CtrlSetup -
//-----------------------------------------------------------------------
void API_CtrlSetup (API_HighFreq_t high_freq,
API_TimeoutEn_t timeout_en,
API_ApiErrEn_t api_err_en,
API_AccessFactor_t access_factor,
API_Timeout_t timeout,
API_Endianism_t endianism,
API_AccessPriority_t access_priority)
{
*(REGISTER_UWORD32*) API_CTRL_ADDR = (high_freq
| timeout_en << API_TIMEOUT_EN_POSBIT
| api_err_en << API_API_ERR_EN_POSBIT
| access_factor << API_ACCESS_FACTOR_POSBIT
| timeout << API_TIMEOUT_POSBIT
| endianism << API_ENDIANISM_POSBIT
| access_priority << API_ACCESS_PRIORITY_POSBIT);
}
//-----------------------------------------------------------------------
// API_DspBootConfig -
//-----------------------------------------------------------------------
void API_DspBootConfig (API_DSPBootMode_t dsp_boot_mode)
{
*(REGISTER_UWORD32*) API_DSP_BOOT_ADDR = (dsp_boot_mode);
}
//-----------------------------------------------------------------------
// API_CtrlSetup -
//-----------------------------------------------------------------------
int API_CtrlReadCompare (API_HighFreq_t high_freq,
API_TimeoutEn_t timeout_en,
API_ApiErrEn_t api_err_en,
API_AccessFactor_t access_factor,
API_Timeout_t timeout,
API_Endianism_t endianism,
API_AccessPriority_t access_priority)
{
UWORD32 value;
value = (high_freq
| timeout_en << API_TIMEOUT_EN_POSBIT
| api_err_en << API_API_ERR_EN_POSBIT
| access_factor << API_ACCESS_FACTOR_POSBIT
| timeout << API_TIMEOUT_POSBIT
| endianism << API_ENDIANISM_POSBIT
| access_priority << API_ACCESS_PRIORITY_POSBIT);
if (value = *(REGISTER_UWORD32*) API_CTRL_ADDR)
return (1);
else
return (0);
}
//----------------------------------------------------------
// NAME : API_TestRWAccessRegs
// DESCRIPTION : Test R/W access on registers
// of DSP Shared Peripherals
//
// PARAMETERS : START_ERROR_CODE
// RETURN VALUE : None
//
// LIMITATIONS : Result must be initialized
// ----------------------------------------------------------
void API_TestRWAccessRegs(UWORD16 START_ERROR_CODE)
{
UWORD16 logresult = TEST_OK;
UWORD16 value;
//-----------------------------------------
//-- READ GPIO registers
//-- Write and Read GPIO REGISTERS
//-- (1) Write a value X to all GPIO register
//-- (2) Read back the value X from all GPIO registers
//-- (3) Write value !(X) to all GPIO register
//-- (4) Read back the value !(X) from all GPIO registers
*(UWORD16 *) DSP_DOR_REG_ADDR = 0x1234;
*(UWORD16 *) DSP_DCR_REG_ADDR = 0x2345;
*(UWORD16 *) DSP_ICR_REG_ADDR = 0x3456;
*(UWORD16 *) DSP_IMR_REG_ADDR = 0x4567;
value = GPIO_LeadReadAllDor();
if (value != 0x1234)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 1);
}
value = GPIO_LeadReadAllDcr();
if (value != 0x2345)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 2);
}
value = GPIO_LeadReadAllIcr();
if (value != 0x3456)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 3);
}
value = GPIO_LeadReadAllImr();
if (value != 0x4567)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 4);
}
*(UWORD16 *) DSP_DOR_REG_ADDR = 0xEDCB;
*(UWORD16 *) DSP_DCR_REG_ADDR = 0xDCBA;
*(UWORD16 *) DSP_ICR_REG_ADDR = 0xCBA9;
*(UWORD16 *) DSP_IMR_REG_ADDR = 0xBA98;
value = GPIO_LeadReadAllDor();
if (value != 0xEDCB)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 5);
}
value = GPIO_LeadReadAllDcr();
if (value != 0xDCBA)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 6);
}
value = GPIO_LeadReadAllIcr();
if (value != 0xCBA9)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 7);
}
value = GPIO_LeadReadAllImr();
if (value != 0xBA98)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 8);
}
//-- Write and Read DSP_ARM Mail Box Registers
//-- DSP can only write to ARM2DSP_INT1 and ARM2DSP_INT1b only when
//-- ARM2DSP_INT1b[0] = '1'. Also ARM2DSP_INT1 has to be written before
//-- ARM2DSP_INT1b register.
// Write a value into ARM2DSP_INT1 and ARM2DSP_INT2, using ARM RHEA
*(UWORD16 *) 0xFFFCF000 = 0x1234;
*(UWORD16 *) 0xFFFCF004 = 0x5678;
//Read back the values using DSP Rhea and compare
value = *(UWORD16 *) ARM2DSP_INT1_REG_ADDR;
if (value != 0x1234)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0010);
}
value = *(UWORD16 *) ARM2DSP_INT1B_REG_ADDR;
if (value != (0x5678 | 0x0001)) /* ARM2DSP mailbox forces LSB to 1 on a ARM_RHEA write */
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0011);
}
//Write opposite values into ARM2DSP_INT1 and ARM2DSP_INT2 using DSP
*(UWORD16 *) ARM2DSP_INT1_REG_ADDR = 0xEDCB;
*(UWORD16 *) ARM2DSP_INT1B_REG_ADDR = 0xA987;
//Read back the value written by DSP Rhea, using DSP Rhea
//Read back the values using DSP Rhea and compare
value = *(UWORD16 *) ARM2DSP_INT1_REG_ADDR;
if (value != 0xEDCB)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0012);
}
value = *(UWORD16 *) ARM2DSP_INT1B_REG_ADDR;
if (value != (0xA987 & 0xFFFE)) /* ARM2DSP mailbox forces LSB to '0', on a DSP Rhea write */
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0013);
}
//Write and Read back from the DSP2ARM registers
*(UWORD16 *) DSP2ARM_INT1_REG_ADDR = 0x3456;
value = *(UWORD16 *) DSP2ARM_INT1_REG_ADDR;
if (value != 0x3456)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0014);
}
*(UWORD16 *) DSP2ARM_INT1B_REG_ADDR = 0x4567;
value = *(UWORD16 *) DSP2ARM_INT1B_REG_ADDR;
if (value != (0x4567 | 0x0001)) /* DSP2ARM1 mailbox forces LSB to '1' on DSP Rhea write */
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0015);
}
*(UWORD16 *) DSP2ARM_INT2_REG_ADDR = 0x5678;
value = *(UWORD16 *) DSP2ARM_INT2_REG_ADDR;
if (value != 0x5678) /* DSP2ARM2 mailbox shifts the data left by 1 bit, LSB is 1? */
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0016);
}
*(UWORD16 *) DSP2ARM_INT2B_REG_ADDR = 0x6789;
value = *(UWORD16 *) DSP2ARM_INT2B_REG_ADDR;
if (value != (0x6789 | 0x0001))
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0017);
}
//-- Write and Read Prefetch Register of PREFETCH_REG
//-- DSP MMU is Write only, so comment out the code -Achuta
/*********
*(UWORD16 *) MEM_DSP_DSPMMU_ADDR = 0x1234;
value = *(UWORD16 *) MEM_DSP_DSPMMU_ADDR;
if ((value & 0x7f) != (0x1234 & 0x7f)) /* 7f is the mask *
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0020);
}
*(UWORD16 *) MEM_DSP_DSPMMU_ADDR = 0xEDCB;
value = *(UWORD16 *) MEM_DSP_DSPMMU_ADDR;
if ((value & 0x7f) != (0xEDCB & 0x7f)) /* 7f is the mask *
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0020);
}
***/
RES_Set( logresult );
RES_Set(RESULT_SEPARATOR);
}
//----------------------------------------------------------
// NAME : API_TestApiMemoryAccessSaram
// DESCRIPTION : Test R/W access on API MEMORY (SARAMs)
// (One access for each SARAM)
//
// PARAMETERS : START_ERROR_CODE
// RETURN VALUE : None
//
// LIMITATIONS : Result must be initialized
// ----------------------------------------------------------
void API_TestApiMemoryAccessSaram(UWORD16 START_ERROR_CODE)
{
UWORD16 logresult = TEST_OK;
//---------------------------------------------------------
//-- 32-bit Write and Read from SARAM's
//-- 2Writes and Reads for each SARAM pair
*(UWORD32*)0xE0010000 = 0x12345678; /* SARAM0 */
*(UWORD32*)0xE0012000 = 0x3456789A; /* SARAM1 */
//read back compare
if (*(UWORD32*)0xE0010000 != 0x12345678)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0000);
}
if (*(UWORD32*)0xE0012000 != 0x3456789A)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0001);
}
*(UWORD32*)0xE0014000 = 0x56789ABC; /* SARAM2 */
*(UWORD32*)0xE0016000 = 0x789ABCDE; /* SARAM3 */
//read back compare
if (*(UWORD32*)0xE0014000 != 0x56789ABC)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0002);
}
if (*(UWORD32*)0xE0016000 != 0x789ABCDE)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0003);
}
*(UWORD32*)0xE0018000 = 0x01234567; /* SARAM4 */
*(UWORD32*)0xE001A000 = 0x3456789A; /* SARAM5 */
//read back compare
if (*(UWORD32*)0xE0018000 != 0x01234567)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0004);
}
if (*(UWORD32*)0xE001A000 != 0x3456789A)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0005);
}
*(UWORD32*)0xE001C000 = 0x12345678; /* SARAM6 */
*(UWORD32*)0xE001E000 = 0x456789AB; /* SARAM7 */
//read back compare
if (*(UWORD32*)0xE001C000 != 0x12345678)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0006);
}
if (*(UWORD32*)0xE001E000 != 0x456789AB)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0007);
}
*(UWORD32*)0xE0020000 = 0x12345678; /* SARAM8 */
*(UWORD32*)0xE0022000 = 0x3456789A; /* SARAM9 */
//read back compare
if (*(UWORD32*)0xE0020000 != 0x12345678)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0008);
}
if (*(UWORD32*)0xE0022000 != 0x3456789A)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0009);
}
*(UWORD32*)0xE0024000 = 0x56789ABC; /* SARAM10 */
*(UWORD32*)0xE0026000 = 0x789ABCDE; /* SARAM11 */
//read back compare
if (*(UWORD32*)0xE0024000 != 0x56789ABC)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x000A);
}
if (*(UWORD32*)0xE0026000 != 0x789ABCDE)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x000B);
}
*(UWORD32*)0xE0028000 = 0x01234567; /* SARAM12 */
*(UWORD32*)0xE002A000 = 0x3456789A; /* SARAM13 */
//read back compare
if (*(UWORD32*)0xE0028000 != 0x01234567)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x000C);
}
if (*(UWORD32*)0xE002A000 != 0x3456789A)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x000D);
}
*(UWORD32*)0xE002C000 = 0x12345678; /* SARAM14 */
*(UWORD32*)0xE002E000 = 0x456789AB; /* SARAM15 */
//read back compare
if (*(UWORD32*)0xE002C000 != 0x12345678)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x000E);
}
if (*(UWORD32*)0xE002E000 != 0x456789AB)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x000F);
}
*(UWORD32*)0xE0030000 = 0x12345678; /* SARAM16 */
*(UWORD32*)0xE0032000 = 0x3456789A; /* SARAM17 */
//read back compare
if (*(UWORD32*)0xE0030000 != 0x12345678)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0010);
}
if (*(UWORD32*)0xE0032000 != 0x3456789A)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0011);
}
*(UWORD32*)0xE0034000 = 0x56789ABC; /* SARAM18 */
*(UWORD32*)0xE0036000 = 0x789ABCDE; /* SARAM19 */
//read back compare
if (*(UWORD32*)0xE0034000 != 0x56789ABC)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0012);
}
if (*(UWORD32*)0xE0036000 != 0x789ABCDE)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0013);
}
*(UWORD32*)0xE0038000 = 0x01234567; /* SARAM20 */
*(UWORD32*)0xE003A000 = 0x3456789A; /* SARAM21 */
//read back compare
if (*(UWORD32*)0xE0038000 != 0x01234567)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0014);
}
if (*(UWORD32*)0xE003A000 != 0x3456789A)
{
logresult = TEST_OK | 0x1;
RES_Set(START_ERROR_CODE + 0x0015);
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