📄 configuration.c

📁 OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器
💻 C
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    BEGIN_RW_TEST(CONFIGURATION_FUNC_MUX_ARM_DMA_D,32);
    //CONFIGURATION_FUNC_MUX_ARM_DMA_D,RESERVED is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_D,CONF_ARM_DMA_REQ_20,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_D,CONF_ARM_DMA_REQ_19,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_D,CONF_ARM_DMA_REQ_18,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_D,CONF_ARM_DMA_REQ_17,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_D,CONF_ARM_DMA_REQ_16,32);
    RW_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_D);
    //CONFIGURATION_FUNC_MUX_ARM_DMA_D,RESERVED is Read Only
    RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_D,CONF_ARM_DMA_REQ_20,32);
    RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_D,CONF_ARM_DMA_REQ_19,32);
    RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_D,CONF_ARM_DMA_REQ_18,32);
    RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_D,CONF_ARM_DMA_REQ_17,32);
    RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_D,CONF_ARM_DMA_REQ_16,32);
    RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_FUNC_MUX_ARM_DMA_D);
    END_RW_TEST();

    BEGIN_RW_TEST(CONFIGURATION_FUNC_MUX_ARM_DMA_E,32);
    //CONFIGURATION_FUNC_MUX_ARM_DMA_E,RESERVED is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_E,CONF_ARM_DMA_REQ_25,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_E,CONF_ARM_DMA_REQ_24,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_E,CONF_ARM_DMA_REQ_23,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_E,CONF_ARM_DMA_REQ_22,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_E,CONF_ARM_DMA_REQ_21,32);
    RW_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_E);
    //CONFIGURATION_FUNC_MUX_ARM_DMA_E,RESERVED is Read Only
    RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_E,CONF_ARM_DMA_REQ_25,32);
    RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_E,CONF_ARM_DMA_REQ_24,32);
    RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_E,CONF_ARM_DMA_REQ_23,32);
    RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_E,CONF_ARM_DMA_REQ_22,32);
    RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_E,CONF_ARM_DMA_REQ_21,32);
    RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_FUNC_MUX_ARM_DMA_E);
    END_RW_TEST();

    BEGIN_RW_TEST(CONFIGURATION_FUNC_MUX_ARM_DMA_F,32);
    //CONFIGURATION_FUNC_MUX_ARM_DMA_F,RESERVED is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_F,CONF_ARM_DMA_REQ_30,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_F,CONF_ARM_DMA_REQ_29,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_F,CONF_ARM_DMA_REQ_28,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_F,CONF_ARM_DMA_REQ_27,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_F,CONF_ARM_DMA_REQ_26,32);
    RW_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_F);
    //CONFIGURATION_FUNC_MUX_ARM_DMA_F,RESERVED is Read Only
    RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_F,CONF_ARM_DMA_REQ_30,32);
    RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_F,CONF_ARM_DMA_REQ_29,32);
    RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_F,CONF_ARM_DMA_REQ_28,32);
    RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_F,CONF_ARM_DMA_REQ_27,32);
    RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_F,CONF_ARM_DMA_REQ_26,32);
    RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_FUNC_MUX_ARM_DMA_F);
    END_RW_TEST();

    BEGIN_RW_TEST(CONFIGURATION_FUNC_MUX_ARM_DMA_G,32);
    //CONFIGURATION_FUNC_MUX_ARM_DMA_G,RESERVED is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_G,CONF_ARM_DMA_REQ_32,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_G,CONF_ARM_DMA_REQ_31,32);
    RW_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_G);
    //CONFIGURATION_FUNC_MUX_ARM_DMA_G,RESERVED is Read Only
    RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_G,CONF_ARM_DMA_REQ_32,32);
    RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_G,CONF_ARM_DMA_REQ_31,32);
    RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_FUNC_MUX_ARM_DMA_G);
    END_RW_TEST();

    BEGIN_RW_TEST(CONFIGURATION_MOD_CONF_CTRL_1,32);
    //CONFIGURATION_MOD_CONF_CTRL_1,RESERVED is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_MOD_CONF_CTRL_1,CONF_PMT_DCB_SELECT,32);
    //CONFIGURATION_MOD_CONF_CTRL_1,RESERVED is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_MOD_CONF_CTRL_1,OCP_INTERCONNECT_GATE_EN_R,32);
    RW_PREPARE_WRITE(CONFIGURATION_MOD_CONF_CTRL_1,CONF_MMC2_CLKFB_SEL_R,32);
    //CONFIGURATION_MOD_CONF_CTRL_1,RESERVED is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_MOD_CONF_CTRL_1,CONF_MCBSP2_CLK_DIS_R,32);
    RW_PREPARE_WRITE(CONFIGURATION_MOD_CONF_CTRL_1,CONF_MCBSP1_CLK_DIS_R,32);
    //CONFIGURATION_MOD_CONF_CTRL_1,RESERVED is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_MOD_CONF_CTRL_1,CONF_MOD_GPTIMER2_CLK_SEL_R,32);
    RW_PREPARE_WRITE(CONFIGURATION_MOD_CONF_CTRL_1,CONF_MOD_GPTIMER1_CLK_SEL_R,32);
    RW_WRITE(CONFIGURATION_MOD_CONF_CTRL_1);
    //CONFIGURATION_MOD_CONF_CTRL_1,RESERVED is Read Only
    RW_TEST_READ(CONFIGURATION_MOD_CONF_CTRL_1,CONF_PMT_DCB_SELECT,32);
    //CONFIGURATION_MOD_CONF_CTRL_1,RESERVED is Read Only
    RW_TEST_READ(CONFIGURATION_MOD_CONF_CTRL_1,OCP_INTERCONNECT_GATE_EN_R,32);
    RW_TEST_READ(CONFIGURATION_MOD_CONF_CTRL_1,CONF_MMC2_CLKFB_SEL_R,32);
    //CONFIGURATION_MOD_CONF_CTRL_1,RESERVED is Read Only
    RW_TEST_READ(CONFIGURATION_MOD_CONF_CTRL_1,CONF_MCBSP2_CLK_DIS_R,32);
    RW_TEST_READ(CONFIGURATION_MOD_CONF_CTRL_1,CONF_MCBSP1_CLK_DIS_R,32);
    //CONFIGURATION_MOD_CONF_CTRL_1,RESERVED is Read Only
    RW_TEST_READ(CONFIGURATION_MOD_CONF_CTRL_1,CONF_MOD_GPTIMER2_CLK_SEL_R,32);
    RW_TEST_READ(CONFIGURATION_MOD_CONF_CTRL_1,CONF_MOD_GPTIMER1_CLK_SEL_R,32);
    RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_MOD_CONF_CTRL_1);
    END_RW_TEST();

    BEGIN_RW_TEST(CONFIGURATION_CONF_STATUS,32);
    //CONFIGURATION_CONF_STATUS,RESERVED is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_CONF_STATUS,FLASH_IF,32);
    //CONFIGURATION_CONF_STATUS,CONF_DEVICE_TYPE_R is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_CONF_STATUS,FLASH_SDRAM_BOOT,32);
    //CONFIGURATION_CONF_STATUS,SYSBOOT_FUSE_SEL is Read Only
    //CONFIGURATION_CONF_STATUS,FLASH_BOOT_CONF is Read Only
    //CONFIGURATION_CONF_STATUS,FLASHING_BYPASS is Read Only
    RW_WRITE(CONFIGURATION_CONF_STATUS);
    //CONFIGURATION_CONF_STATUS,RESERVED is Read Only
    RW_TEST_READ(CONFIGURATION_CONF_STATUS,FLASH_IF,32);
    //CONFIGURATION_CONF_STATUS,CONF_DEVICE_TYPE_R is Read Only
    RW_TEST_READ(CONFIGURATION_CONF_STATUS,FLASH_SDRAM_BOOT,32);
    //CONFIGURATION_CONF_STATUS,SYSBOOT_FUSE_SEL is Read Only
    //CONFIGURATION_CONF_STATUS,FLASH_BOOT_CONF is Read Only
    //CONFIGURATION_CONF_STATUS,FLASHING_BYPASS is Read Only
    RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_CONF_STATUS);
    END_RW_TEST();

    BEGIN_RW_TEST(CONFIGURATION_RESET_CONTROL,32);
    //CONFIGURATION_RESET_CONTROL,RESERVED is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_RESET_CONTROL,CONF_RNG_IDLE_MODE,32);
    //RW_PREPARE_WRITE(CONFIGURATION_RESET_CONTROL,RESERVED,32);
    RW_PREPARE_WRITE(CONFIGURATION_RESET_CONTROL,CONF_UWIRE_RESET_R,32);
    RW_PREPARE_WRITE(CONFIGURATION_RESET_CONTROL,CONF_OSTIMER_RESET_R,32);
    //CONFIGURATION_RESET_CONTROL,RESERVED is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_RESET_CONTROL,CONF_OCP_RESET_R,32);
    RW_WRITE(CONFIGURATION_RESET_CONTROL);
    //CONFIGURATION_RESET_CONTROL,RESERVED is Read Only
    RW_TEST_READ(CONFIGURATION_RESET_CONTROL,CONF_RNG_IDLE_MODE,32);
    //RW_TEST_READ(CONFIGURATION_RESET_CONTROL,RESERVED,32);
    RW_TEST_READ(CONFIGURATION_RESET_CONTROL,CONF_UWIRE_RESET_R,32);
    RW_TEST_READ(CONFIGURATION_RESET_CONTROL,CONF_OSTIMER_RESET_R,32);
    //CONFIGURATION_RESET_CONTROL,RESERVED is Read Only
    RW_TEST_READ(CONFIGURATION_RESET_CONTROL,CONF_OCP_RESET_R,32);
    RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_RESET_CONTROL);
    END_RW_TEST();

    BEGIN_RW_TEST(CONFIGURATION_CONF_OCPI_CTRL,32);
    //CONFIGURATION_CONF_OCPI_CTRL,RESERVED is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_CONF_OCPI_CTRL,EN_BUFFER_USB,32);
    //CONFIGURATION_CONF_OCPI_CTRL,RESERVED is Read Only
    RW_WRITE(CONFIGURATION_CONF_OCPI_CTRL);
    //CONFIGURATION_CONF_OCPI_CTRL,RESERVED is Read Only
    RW_TEST_READ(CONFIGURATION_CONF_OCPI_CTRL,EN_BUFFER_USB,32);
    //CONFIGURATION_CONF_OCPI_CTRL,RESERVED is Read Only
    RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_CONF_OCPI_CTRL);
    END_RW_TEST();

    BEGIN_RW_TEST(CONFIGURATION_FUNC1_ARMPERGATE_CLK,32);
    //CONFIGURATION_FUNC1_ARMPERGATE_CLK,RESERVED is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_FUNC1_ARMPERGATE_CLK,UART_CONF2,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC1_ARMPERGATE_CLK,UART_CONF1,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC1_ARMPERGATE_CLK,UART_CONF0,32);
    //RW_PREPARE_WRITE(CONFIGURATION_FUNC1_ARMPERGATE_CLK,RESERVED,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC1_ARMPERGATE_CLK,GPIO_CONF2,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC1_ARMPERGATE_CLK,GPIO_CONF1,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC1_ARMPERGATE_CLK,GPIO_CONF0,32);
    //CONFIGURATION_FUNC1_ARMPERGATE_CLK,RESERVED is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_FUNC1_ARMPERGATE_CLK,DMTIMER_CONF1,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC1_ARMPERGATE_CLK,DMTIMER_CONF0,32);
    RW_WRITE(CONFIGURATION_FUNC1_ARMPERGATE_CLK);
    //CONFIGURATION_FUNC1_ARMPERGATE_CLK,RESERVED is Read Only
    RW_TEST_READ(CONFIGURATION_FUNC1_ARMPERGATE_CLK,UART_CONF2,32);
    RW_TEST_READ(CONFIGURATION_FUNC1_ARMPERGATE_CLK,UART_CONF1,32);
    RW_TEST_READ(CONFIGURATION_FUNC1_ARMPERGATE_CLK,UART_CONF0,32);
    //RW_TEST_READ(CONFIGURATION_FUNC1_ARMPERGATE_CLK,RESERVED,32);
    RW_TEST_READ(CONFIGURATION_FUNC1_ARMPERGATE_CLK,GPIO_CONF2,32);
    RW_TEST_READ(CONFIGURATION_FUNC1_ARMPERGATE_CLK,GPIO_CONF1,32);
    RW_TEST_READ(CONFIGURATION_FUNC1_ARMPERGATE_CLK,GPIO_CONF0,32);
    //CONFIGURATION_FUNC1_ARMPERGATE_CLK,RESERVED is Read Only
    RW_TEST_READ(CONFIGURATION_FUNC1_ARMPERGATE_CLK,DMTIMER_CONF1,32);
    RW_TEST_READ(CONFIGURATION_FUNC1_ARMPERGATE_CLK,DMTIMER_CONF0,32);
    RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_FUNC1_ARMPERGATE_CLK);
    END_RW_TEST();

    BEGIN_RW_TEST(CONFIGURATION_FUNC2_ARMPERGATE_CLK,32);
    //CONFIGURATION_FUNC2_ARMPERGATE_CLK,RESERVED is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_FUNC2_ARMPERGATE_CLK,NAND_FLASH_DIS,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC2_ARMPERGATE_CLK,UART_DIS2,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC2_ARMPERGATE_CLK,UART_DIS1,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC2_ARMPERGATE_CLK,UART_DIS0,32);
    //CONFIGURATION_FUNC2_ARMPERGATE_CLK,RESERVED is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_FUNC2_ARMPERGATE_CLK,GPIO_DIS2,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC2_ARMPERGATE_CLK,GPIO_DIS1,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC2_ARMPERGATE_CLK,GPIO_DIS0,32);
    //CONFIGURATION_FUNC2_ARMPERGATE_CLK,RESERVED is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_FUNC2_ARMPERGATE_CLK,DMTIMER_DIS1,32);
    RW_PREPARE_WRITE(CONFIGURATION_FUNC2_ARMPERGATE_CLK,DMTIMER_DIS0,32);
    RW_WRITE(CONFIGURATION_FUNC2_ARMPERGATE_CLK);
    //CONFIGURATION_FUNC2_ARMPERGATE_CLK,RESERVED is Read Only
    RW_TEST_READ(CONFIGURATION_FUNC2_ARMPERGATE_CLK,NAND_FLASH_DIS,32);
    RW_TEST_READ(CONFIGURATION_FUNC2_ARMPERGATE_CLK,UART_DIS2,32);
    RW_TEST_READ(CONFIGURATION_FUNC2_ARMPERGATE_CLK,UART_DIS1,32);
    RW_TEST_READ(CONFIGURATION_FUNC2_ARMPERGATE_CLK,UART_DIS0,32);
    //CONFIGURATION_FUNC2_ARMPERGATE_CLK,RESERVED is Read Only
    RW_TEST_READ(CONFIGURATION_FUNC2_ARMPERGATE_CLK,GPIO_DIS2,32);
    RW_TEST_READ(CONFIGURATION_FUNC2_ARMPERGATE_CLK,GPIO_DIS1,32);
    RW_TEST_READ(CONFIGURATION_FUNC2_ARMPERGATE_CLK,GPIO_DIS0,32);
    //CONFIGURATION_FUNC2_ARMPERGATE_CLK,RESERVED is Read Only
    RW_TEST_READ(CONFIGURATION_FUNC2_ARMPERGATE_CLK,DMTIMER_DIS1,32);
    RW_TEST_READ(CONFIGURATION_FUNC2_ARMPERGATE_CLK,DMTIMER_DIS0,32);
    RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_FUNC2_ARMPERGATE_CLK);
    END_RW_TEST();

    BEGIN_RW_TEST(CONFIGURATION_SPARE_REG,32);
    //CONFIGURATION_SPARE_REG,RESERVED is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_SPARE_REG,SPARE_REG3,32);
    RW_PREPARE_WRITE(CONFIGURATION_SPARE_REG,SPARE_REG2,32);
    RW_PREPARE_WRITE(CONFIGURATION_SPARE_REG,SPARE_REG1,32);
    RW_WRITE(CONFIGURATION_SPARE_REG);
    //CONFIGURATION_SPARE_REG,RESERVED is Read Only
    RW_TEST_READ(CONFIGURATION_SPARE_REG,SPARE_REG3,32);
    RW_TEST_READ(CONFIGURATION_SPARE_REG,SPARE_REG2,32);
    RW_TEST_READ(CONFIGURATION_SPARE_REG,SPARE_REG1,32);
    RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_SPARE_REG);
    END_RW_TEST();

  END_ACCESS_MODULE();

}
上一页 1 2 34
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