📄 configuration.c
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RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_SECCTRL_2);
END_RW_TEST();
BEGIN_RW_TEST(CONFIGURATION_SEC_TEST_CTRL,32);
//CONFIGURATION_SEC_TEST_CTRL,RESERVED is Read Only
RW_PREPARE_WRITE(CONFIGURATION_SEC_TEST_CTRL,OBSERVABILITY_DISABLE,32);
RW_PREPARE_WRITE(CONFIGURATION_SEC_TEST_CTRL,DMLED_SYSTEM_EN,32);
RW_PREPARE_WRITE(CONFIGURATION_SEC_TEST_CTRL,BCM_WR_DISABLE,32);
RW_PREPARE_WRITE(CONFIGURATION_SEC_TEST_CTRL,SEC_TEST_WR_DISABLE,32);
RW_WRITE(CONFIGURATION_SEC_TEST_CTRL);
//CONFIGURATION_SEC_TEST_CTRL,RESERVED is Read Only
RW_TEST_READ(CONFIGURATION_SEC_TEST_CTRL,OBSERVABILITY_DISABLE,32);
RW_TEST_READ(CONFIGURATION_SEC_TEST_CTRL,DMLED_SYSTEM_EN,32);
RW_TEST_READ(CONFIGURATION_SEC_TEST_CTRL,BCM_WR_DISABLE,32);
RW_TEST_READ(CONFIGURATION_SEC_TEST_CTRL,SEC_TEST_WR_DISABLE,32);
RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_SEC_TEST_CTRL);
END_RW_TEST();
BEGIN_RW_TEST(CONFIGURATION_SEC_TAP_CTRL,32);
//CONFIGURATION_SEC_TAP_CTRL,RESERVED is Read Only
RW_PREPARE_WRITE(CONFIGURATION_SEC_TAP_CTRL,EFUSE_TAP_ENABLE,32);
RW_PREPARE_WRITE(CONFIGURATION_SEC_TAP_CTRL,CHIPLEVEL_TAP_ENABLE,32);
RW_PREPARE_WRITE(CONFIGURATION_SEC_TAP_CTRL,DSP_TAP_ENABLE,32);
RW_PREPARE_WRITE(CONFIGURATION_SEC_TAP_CTRL,MPU_TAP_ENABLE,32);
RW_PREPARE_WRITE(CONFIGURATION_SEC_TAP_CTRL,SEC_TAP_WR_DISABLE,32);
RW_WRITE(CONFIGURATION_SEC_TAP_CTRL);
//CONFIGURATION_SEC_TAP_CTRL,RESERVED is Read Only
RW_TEST_READ(CONFIGURATION_SEC_TAP_CTRL,EFUSE_TAP_ENABLE,32);
RW_TEST_READ(CONFIGURATION_SEC_TAP_CTRL,CHIPLEVEL_TAP_ENABLE,32);
RW_TEST_READ(CONFIGURATION_SEC_TAP_CTRL,DSP_TAP_ENABLE,32);
RW_TEST_READ(CONFIGURATION_SEC_TAP_CTRL,MPU_TAP_ENABLE,32);
RW_TEST_READ(CONFIGURATION_SEC_TAP_CTRL,SEC_TAP_WR_DISABLE,32);
RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_SEC_TAP_CTRL);
END_RW_TEST();
BEGIN_RW_TEST(CONFIGURATION_SEC_EMU_CTRL,32);
//CONFIGURATION_SEC_EMU_CTRL,RESERVED is Read Only
RW_PREPARE_WRITE(CONFIGURATION_SEC_EMU_CTRL,ETM_ENABLE,32);
RW_PREPARE_WRITE(CONFIGURATION_SEC_EMU_CTRL,CTOOLS_ENABLE,32);
RW_PREPARE_WRITE(CONFIGURATION_SEC_EMU_CTRL,MPU_DBG_ENABLE,32);
RW_PREPARE_WRITE(CONFIGURATION_SEC_EMU_CTRL,MPU_SEC_DBG_ENABLE,32);
RW_PREPARE_WRITE(CONFIGURATION_SEC_EMU_CTRL,SEC_EMU_WR_DISABLE,32);
RW_WRITE(CONFIGURATION_SEC_EMU_CTRL);
//CONFIGURATION_SEC_EMU_CTRL,RESERVED is Read Only
RW_TEST_READ(CONFIGURATION_SEC_EMU_CTRL,ETM_ENABLE,32);
RW_TEST_READ(CONFIGURATION_SEC_EMU_CTRL,CTOOLS_ENABLE,32);
RW_TEST_READ(CONFIGURATION_SEC_EMU_CTRL,MPU_DBG_ENABLE,32);
RW_TEST_READ(CONFIGURATION_SEC_EMU_CTRL,MPU_SEC_DBG_ENABLE,32);
RW_TEST_READ(CONFIGURATION_SEC_EMU_CTRL,SEC_EMU_WR_DISABLE,32);
RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_SEC_EMU_CTRL);
END_RW_TEST();
BEGIN_RW_TEST(CONFIGURATION_VOLTAGE_CTRL_0,32);
//RW_PREPARE_WRITE(CONFIGURATION_VOLTAGE_CTRL_0,RESERVED,32);
RW_PREPARE_WRITE(CONFIGURATION_VOLTAGE_CTRL_0,SUBLVDS_CONF_VALID_R,32);
//RW_PREPARE_WRITE(CONFIGURATION_VOLTAGE_CTRL_0,RESERVED,32);
RW_PREPARE_WRITE(CONFIGURATION_VOLTAGE_CTRL_0,MMC1_PWRDN,32);
RW_PREPARE_WRITE(CONFIGURATION_VOLTAGE_CTRL_0,USIM_PWRDN,32);
RW_PREPARE_WRITE(CONFIGURATION_VOLTAGE_CTRL_0,MMC_PBIAS_CTL,32);
RW_PREPARE_WRITE(CONFIGURATION_VOLTAGE_CTRL_0,USIM_PBIAS_CTL,32);
RW_WRITE(CONFIGURATION_VOLTAGE_CTRL_0);
//RW_TEST_READ(CONFIGURATION_VOLTAGE_CTRL_0,RESERVED,32);
RW_TEST_READ(CONFIGURATION_VOLTAGE_CTRL_0,SUBLVDS_CONF_VALID_R,32);
//RW_TEST_READ(CONFIGURATION_VOLTAGE_CTRL_0,RESERVED,32);
RW_TEST_READ(CONFIGURATION_VOLTAGE_CTRL_0,MMC1_PWRDN,32);
RW_TEST_READ(CONFIGURATION_VOLTAGE_CTRL_0,USIM_PWRDN,32);
RW_TEST_READ(CONFIGURATION_VOLTAGE_CTRL_0,MMC_PBIAS_CTL,32);
RW_TEST_READ(CONFIGURATION_VOLTAGE_CTRL_0,USIM_PBIAS_CTL,32);
RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_VOLTAGE_CTRL_0);
END_RW_TEST();
BEGIN_RW_TEST(CONFIGURATION_USB_TRANSCEIVER_CTRL,32);
//CONFIGURATION_USB_TRANSCEIVER_CTRL,RESERVED is Read Only
RW_PREPARE_WRITE(CONFIGURATION_USB_TRANSCEIVER_CTRL,USB2_WRMODE,32);
RW_PREPARE_WRITE(CONFIGURATION_USB_TRANSCEIVER_CTRL,USB1_WRMODE,32);
RW_PREPARE_WRITE(CONFIGURATION_USB_TRANSCEIVER_CTRL,USB0_WRMODE,32);
//RW_PREPARE_WRITE(CONFIGURATION_USB_TRANSCEIVER_CTRL,RESERVED,32);
RW_WRITE(CONFIGURATION_USB_TRANSCEIVER_CTRL);
//CONFIGURATION_USB_TRANSCEIVER_CTRL,RESERVED is Read Only
RW_TEST_READ(CONFIGURATION_USB_TRANSCEIVER_CTRL,USB2_WRMODE,32);
RW_TEST_READ(CONFIGURATION_USB_TRANSCEIVER_CTRL,USB1_WRMODE,32);
RW_TEST_READ(CONFIGURATION_USB_TRANSCEIVER_CTRL,USB0_WRMODE,32);
//RW_TEST_READ(CONFIGURATION_USB_TRANSCEIVER_CTRL,RESERVED,32);
RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_USB_TRANSCEIVER_CTRL);
END_RW_TEST();
BEGIN_RW_TEST(CONFIGURATION_TEST_DBG_CTRL_0,32);
//RW_PREPARE_WRITE(CONFIGURATION_TEST_DBG_CTRL_0,RESERVED,32);
RW_PREPARE_WRITE(CONFIGURATION_TEST_DBG_CTRL_0,CONF_RNG_TEST_OSC,32);
RW_PREPARE_WRITE(CONFIGURATION_TEST_DBG_CTRL_0,CONF_RNG_SELECT_OSC,32);
//RW_PREPARE_WRITE(CONFIGURATION_TEST_DBG_CTRL_0,RESERVED,32);
RW_PREPARE_WRITE(CONFIGURATION_TEST_DBG_CTRL_0,CONF_DPLL_EXT_SEL,32);
//CONFIGURATION_TEST_DBG_CTRL_0,RESERVED is Read Only
RW_WRITE(CONFIGURATION_TEST_DBG_CTRL_0);
//RW_TEST_READ(CONFIGURATION_TEST_DBG_CTRL_0,RESERVED,32);
RW_TEST_READ(CONFIGURATION_TEST_DBG_CTRL_0,CONF_RNG_TEST_OSC,32);
RW_TEST_READ(CONFIGURATION_TEST_DBG_CTRL_0,CONF_RNG_SELECT_OSC,32);
//RW_TEST_READ(CONFIGURATION_TEST_DBG_CTRL_0,RESERVED,32);
RW_TEST_READ(CONFIGURATION_TEST_DBG_CTRL_0,CONF_DPLL_EXT_SEL,32);
//CONFIGURATION_TEST_DBG_CTRL_0,RESERVED is Read Only
RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_TEST_DBG_CTRL_0);
END_RW_TEST();
BEGIN_RW_TEST(CONFIGURATION_MOD_CONF_CTRL_0,32);
//RW_PREPARE_WRITE(CONFIGURATION_MOD_CONF_CTRL_0,RESERVED,32);
RW_PREPARE_WRITE(CONFIGURATION_MOD_CONF_CTRL_0,CONF_MOD_MCBSP1DIG_RF_CLKSEL,32);
RW_PREPARE_WRITE(CONFIGURATION_MOD_CONF_CTRL_0,CONF_MCBSP1_MOD,32);
RW_PREPARE_WRITE(CONFIGURATION_MOD_CONF_CTRL_0,CONF_MOD_MCBSP1_CLKS_SEL_R,32);
RW_PREPARE_WRITE(CONFIGURATION_MOD_CONF_CTRL_0,MPU_NRST_CTL,32);
//RW_PREPARE_WRITE(CONFIGURATION_MOD_CONF_CTRL_0,RESERVED,32);
RW_PREPARE_WRITE(CONFIGURATION_MOD_CONF_CTRL_0,CAMERA_IF,32);
RW_PREPARE_WRITE(CONFIGURATION_MOD_CONF_CTRL_0,CONF_MOD_MCBSP1_CLK_SEL_R,32);
RW_PREPARE_WRITE(CONFIGURATION_MOD_CONF_CTRL_0,CONF_MOD_MMC2_CLK_SEL_R,32);
RW_PREPARE_WRITE(CONFIGURATION_MOD_CONF_CTRL_0,ISRAM_AUTO_IDLE,32);
//RW_PREPARE_WRITE(CONFIGURATION_MOD_CONF_CTRL_0,RESERVED,32);
RW_WRITE(CONFIGURATION_MOD_CONF_CTRL_0);
//RW_TEST_READ(CONFIGURATION_MOD_CONF_CTRL_0,RESERVED,32);
RW_TEST_READ(CONFIGURATION_MOD_CONF_CTRL_0,CONF_MOD_MCBSP1DIG_RF_CLKSEL,32);
RW_TEST_READ(CONFIGURATION_MOD_CONF_CTRL_0,CONF_MCBSP1_MOD,32);
RW_TEST_READ(CONFIGURATION_MOD_CONF_CTRL_0,CONF_MOD_MCBSP1_CLKS_SEL_R,32);
RW_TEST_READ(CONFIGURATION_MOD_CONF_CTRL_0,MPU_NRST_CTL,32);
//RW_TEST_READ(CONFIGURATION_MOD_CONF_CTRL_0,RESERVED,32);
RW_TEST_READ(CONFIGURATION_MOD_CONF_CTRL_0,CAMERA_IF,32);
RW_TEST_READ(CONFIGURATION_MOD_CONF_CTRL_0,CONF_MOD_MCBSP1_CLK_SEL_R,32);
RW_TEST_READ(CONFIGURATION_MOD_CONF_CTRL_0,CONF_MOD_MMC2_CLK_SEL_R,32);
RW_TEST_READ(CONFIGURATION_MOD_CONF_CTRL_0,ISRAM_AUTO_IDLE,32);
//RW_TEST_READ(CONFIGURATION_MOD_CONF_CTRL_0,RESERVED,32);
RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_MOD_CONF_CTRL_0);
END_RW_TEST();
BEGIN_RW_TEST(CONFIGURATION_FUNC_MUX_DSP_DMA_A,32);
//RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_DSP_DMA_A,RESERVED,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_DSP_DMA_A,CONF_DSP_DMA_REQ_06,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_DSP_DMA_A,CONF_DSP_DMA_REQ_05,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_DSP_DMA_A,CONF_DSP_DMA_REQ_04,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_DSP_DMA_A,CONF_DSP_DMA_REQ_03,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_DSP_DMA_A,CONF_DSP_DMA_REQ_02,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_DSP_DMA_A,CONF_DSP_DMA_REQ_01,32);
RW_WRITE(CONFIGURATION_FUNC_MUX_DSP_DMA_A);
//RW_TEST_READ(CONFIGURATION_FUNC_MUX_DSP_DMA_A,RESERVED,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_DSP_DMA_A,CONF_DSP_DMA_REQ_06,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_DSP_DMA_A,CONF_DSP_DMA_REQ_05,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_DSP_DMA_A,CONF_DSP_DMA_REQ_04,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_DSP_DMA_A,CONF_DSP_DMA_REQ_03,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_DSP_DMA_A,CONF_DSP_DMA_REQ_02,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_DSP_DMA_A,CONF_DSP_DMA_REQ_01,32);
RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_FUNC_MUX_DSP_DMA_A);
END_RW_TEST();
BEGIN_RW_TEST(CONFIGURATION_FUNC_MUX_DSP_DMA_B,32);
//RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_DSP_DMA_B,RESERVED,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_DSP_DMA_B,CONF_DSP_DMA_REQ_12,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_DSP_DMA_B,CONF_DSP_DMA_REQ_11,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_DSP_DMA_B,CONF_DSP_DMA_REQ_10,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_DSP_DMA_B,CONF_DSP_DMA_REQ_09,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_DSP_DMA_B,CONF_DSP_DMA_REQ_08,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_DSP_DMA_B,CONF_DSP_DMA_REQ_07,32);
RW_WRITE(CONFIGURATION_FUNC_MUX_DSP_DMA_B);
//RW_TEST_READ(CONFIGURATION_FUNC_MUX_DSP_DMA_B,RESERVED,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_DSP_DMA_B,CONF_DSP_DMA_REQ_12,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_DSP_DMA_B,CONF_DSP_DMA_REQ_11,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_DSP_DMA_B,CONF_DSP_DMA_REQ_10,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_DSP_DMA_B,CONF_DSP_DMA_REQ_09,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_DSP_DMA_B,CONF_DSP_DMA_REQ_08,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_DSP_DMA_B,CONF_DSP_DMA_REQ_07,32);
RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_FUNC_MUX_DSP_DMA_B);
END_RW_TEST();
BEGIN_RW_TEST(CONFIGURATION_FUNC_MUX_ARM_DMA_A,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_A,CONF_ARM_DMA_REQ_05,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_A,CONF_ARM_DMA_REQ_04,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_A,CONF_ARM_DMA_REQ_03,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_A,CONF_ARM_DMA_REQ_02,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_A,CONF_ARM_DMA_REQ_01,32);
RW_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_A);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_A,CONF_ARM_DMA_REQ_05,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_A,CONF_ARM_DMA_REQ_04,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_A,CONF_ARM_DMA_REQ_03,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_A,CONF_ARM_DMA_REQ_02,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_A,CONF_ARM_DMA_REQ_01,32);
RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_FUNC_MUX_ARM_DMA_A);
END_RW_TEST();
BEGIN_RW_TEST(CONFIGURATION_FUNC_MUX_ARM_DMA_B,32);
//CONFIGURATION_FUNC_MUX_ARM_DMA_B,RESERVED is Read Only
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_B,CONF_ARM_DMA_REQ_10,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_B,CONF_ARM_DMA_REQ_09,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_B,CONF_ARM_DMA_REQ_08,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_B,CONF_ARM_DMA_REQ_07,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_B,CONF_ARM_DMA_REQ_06,32);
RW_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_B);
//CONFIGURATION_FUNC_MUX_ARM_DMA_B,RESERVED is Read Only
RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_B,CONF_ARM_DMA_REQ_10,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_B,CONF_ARM_DMA_REQ_09,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_B,CONF_ARM_DMA_REQ_08,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_B,CONF_ARM_DMA_REQ_07,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_B,CONF_ARM_DMA_REQ_06,32);
RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_FUNC_MUX_ARM_DMA_B);
END_RW_TEST();
BEGIN_RW_TEST(CONFIGURATION_FUNC_MUX_ARM_DMA_C,32);
//CONFIGURATION_FUNC_MUX_ARM_DMA_C,RESERVED is Read Only
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_C,CONF_ARM_DMA_REQ_15,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_C,CONF_ARM_DMA_REQ_14,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_C,CONF_ARM_DMA_REQ_13,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_C,CONF_ARM_DMA_REQ_12,32);
RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_C,CONF_ARM_DMA_REQ_11,32);
RW_WRITE(CONFIGURATION_FUNC_MUX_ARM_DMA_C);
//CONFIGURATION_FUNC_MUX_ARM_DMA_C,RESERVED is Read Only
RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_C,CONF_ARM_DMA_REQ_15,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_C,CONF_ARM_DMA_REQ_14,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_C,CONF_ARM_DMA_REQ_13,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_C,CONF_ARM_DMA_REQ_12,32);
RW_TEST_READ(CONFIGURATION_FUNC_MUX_ARM_DMA_C,CONF_ARM_DMA_REQ_11,32);
RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_FUNC_MUX_ARM_DMA_C);
END_RW_TEST();
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