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📄 configuration.c

📁 OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器
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    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_B,CONF_ARM_DMA_REQ_07,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_B,CONF_ARM_DMA_REQ_06,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_FUNC_MUX_ARM_DMA_C,32);
    //TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_C,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_C,CONF_ARM_DMA_REQ_15,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_C,CONF_ARM_DMA_REQ_14,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_C,CONF_ARM_DMA_REQ_13,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_C,CONF_ARM_DMA_REQ_12,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_C,CONF_ARM_DMA_REQ_11,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_FUNC_MUX_ARM_DMA_D,32);
    //TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_D,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_D,CONF_ARM_DMA_REQ_20,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_D,CONF_ARM_DMA_REQ_19,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_D,CONF_ARM_DMA_REQ_18,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_D,CONF_ARM_DMA_REQ_17,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_D,CONF_ARM_DMA_REQ_16,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_FUNC_MUX_ARM_DMA_E,32);
    //TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_E,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_E,CONF_ARM_DMA_REQ_25,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_E,CONF_ARM_DMA_REQ_24,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_E,CONF_ARM_DMA_REQ_23,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_E,CONF_ARM_DMA_REQ_22,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_E,CONF_ARM_DMA_REQ_21,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_FUNC_MUX_ARM_DMA_F,32);
    //TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_F,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_F,CONF_ARM_DMA_REQ_30,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_F,CONF_ARM_DMA_REQ_29,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_F,CONF_ARM_DMA_REQ_28,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_F,CONF_ARM_DMA_REQ_27,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_F,CONF_ARM_DMA_REQ_26,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_FUNC_MUX_ARM_DMA_G,32);
    //TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_G,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_G,CONF_ARM_DMA_REQ_32,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_G,CONF_ARM_DMA_REQ_31,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_MOD_CONF_CTRL_1,32);
    //TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_1,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_1,CONF_PMT_DCB_SELECT,32);
    //TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_1,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_1,OCP_INTERCONNECT_GATE_EN_R,32);
    TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_1,CONF_MMC2_CLKFB_SEL_R,32);
    //TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_1,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_1,CONF_MCBSP2_CLK_DIS_R,32);
    TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_1,CONF_MCBSP1_CLK_DIS_R,32);
    //TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_1,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_1,CONF_MOD_GPTIMER2_CLK_SEL_R,32);
    TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_1,CONF_MOD_GPTIMER1_CLK_SEL_R,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_CONF_STATUS,32);
    //TEST_FIELD_RESET(CONFIGURATION_CONF_STATUS,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_CONF_STATUS,FLASH_IF,32);
    TEST_FIELD_RESET(CONFIGURATION_CONF_STATUS,CONF_DEVICE_TYPE_R,32);
    TEST_FIELD_RESET(CONFIGURATION_CONF_STATUS,FLASH_SDRAM_BOOT,32);
    TEST_FIELD_RESET(CONFIGURATION_CONF_STATUS,SYSBOOT_FUSE_SEL,32);
    TEST_FIELD_RESET(CONFIGURATION_CONF_STATUS,FLASH_BOOT_CONF,32);
    TEST_FIELD_RESET(CONFIGURATION_CONF_STATUS,FLASHING_BYPASS,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_RESET_CONTROL,32);
    //TEST_FIELD_RESET(CONFIGURATION_RESET_CONTROL,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_RESET_CONTROL,CONF_RNG_IDLE_MODE,32);
    //TEST_FIELD_RESET(CONFIGURATION_RESET_CONTROL,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_RESET_CONTROL,CONF_UWIRE_RESET_R,32);
    TEST_FIELD_RESET(CONFIGURATION_RESET_CONTROL,CONF_OSTIMER_RESET_R,32);
    //TEST_FIELD_RESET(CONFIGURATION_RESET_CONTROL,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_RESET_CONTROL,CONF_OCP_RESET_R,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_CONF_OCPI_CTRL,32);
    //TEST_FIELD_RESET(CONFIGURATION_CONF_OCPI_CTRL,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_CONF_OCPI_CTRL,EN_BUFFER_USB,32);
    //TEST_FIELD_RESET(CONFIGURATION_CONF_OCPI_CTRL,RESERVED,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_FUNC1_ARMPERGATE_CLK,32);
    //TEST_FIELD_RESET(CONFIGURATION_FUNC1_ARMPERGATE_CLK,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC1_ARMPERGATE_CLK,UART_CONF2,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC1_ARMPERGATE_CLK,UART_CONF1,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC1_ARMPERGATE_CLK,UART_CONF0,32);
    //TEST_FIELD_RESET(CONFIGURATION_FUNC1_ARMPERGATE_CLK,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC1_ARMPERGATE_CLK,GPIO_CONF2,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC1_ARMPERGATE_CLK,GPIO_CONF1,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC1_ARMPERGATE_CLK,GPIO_CONF0,32);
    //TEST_FIELD_RESET(CONFIGURATION_FUNC1_ARMPERGATE_CLK,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC1_ARMPERGATE_CLK,DMTIMER_CONF1,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC1_ARMPERGATE_CLK,DMTIMER_CONF0,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_FUNC2_ARMPERGATE_CLK,32);
    //TEST_FIELD_RESET(CONFIGURATION_FUNC2_ARMPERGATE_CLK,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC2_ARMPERGATE_CLK,NAND_FLASH_DIS,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC2_ARMPERGATE_CLK,UART_DIS2,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC2_ARMPERGATE_CLK,UART_DIS1,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC2_ARMPERGATE_CLK,UART_DIS0,32);
    //TEST_FIELD_RESET(CONFIGURATION_FUNC2_ARMPERGATE_CLK,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC2_ARMPERGATE_CLK,GPIO_DIS2,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC2_ARMPERGATE_CLK,GPIO_DIS1,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC2_ARMPERGATE_CLK,GPIO_DIS0,32);
    //TEST_FIELD_RESET(CONFIGURATION_FUNC2_ARMPERGATE_CLK,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC2_ARMPERGATE_CLK,DMTIMER_DIS1,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC2_ARMPERGATE_CLK,DMTIMER_DIS0,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_SPARE_REG,32);
    //TEST_FIELD_RESET(CONFIGURATION_SPARE_REG,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_SPARE_REG,SPARE_REG3,32);
    TEST_FIELD_RESET(CONFIGURATION_SPARE_REG,SPARE_REG2,32);
    TEST_FIELD_RESET(CONFIGURATION_SPARE_REG,SPARE_REG1,32);
    END_RESET_TEST();

  END_RESET_MODULE();

}

//---------------------------------------------------------------------
// NAME        : CONFIGURATION_TestRegistersAccess
//
// DESCRIPTION : Test the access to CONFIGURATION registers
//
// PARAMETERS  : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void CONFIGURATION_TestRegistersAccess(void)
{
  BEGIN_ACCESS_MODULE();

    BEGIN_RW_TEST(CONFIGURATION_FUNC_MUX_CTRL_0,32);
    //CONFIGURATION_FUNC_MUX_CTRL_0,RESERVED is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_FUNC_MUX_CTRL_0,LRU_SEL,32);
    //CONFIGURATION_FUNC_MUX_CTRL_0,RESERVED is Read Only
    RW_WRITE(CONFIGURATION_FUNC_MUX_CTRL_0);
    //CONFIGURATION_FUNC_MUX_CTRL_0,RESERVED is Read Only
    RW_TEST_READ(CONFIGURATION_FUNC_MUX_CTRL_0,LRU_SEL,32);
    //CONFIGURATION_FUNC_MUX_CTRL_0,RESERVED is Read Only
    RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_FUNC_MUX_CTRL_0);
    END_RW_TEST();

    BEGIN_RW_TEST(CONFIGURATION_COMP_MODE_CTRL_0,32);
    //CONFIGURATION_COMP_MODE_CTRL_0,RESERVED is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_COMP_MODE_CTRL_0,CONF_MUX_EN_R,32);
    RW_WRITE(CONFIGURATION_COMP_MODE_CTRL_0);
    //CONFIGURATION_COMP_MODE_CTRL_0,RESERVED is Read Only
    RW_TEST_READ(CONFIGURATION_COMP_MODE_CTRL_0,CONF_MUX_EN_R,32);
    RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_COMP_MODE_CTRL_0);
    END_RW_TEST();

    BEGIN_RW_TEST(CONFIGURATION_SECCTRL_1,32);
    //CONFIGURATION_SECCTRL_1,RESERVED is Read Only
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_1,TM_PROTECT_EN,32);
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_1,SEC_MODE_INIT_DONE,32);
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_1,RNG_NS_ENABLE,32);
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_1,PKA_NS_ENABLE,32);
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_1,AES_NS_ENABLE,32);
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_1,DES_NS_ENABLE,32);
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_1,SHA_NS_ENABLE,32);
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_1,SEC_CTRL1_WR_DISABLE,32);
    RW_WRITE(CONFIGURATION_SECCTRL_1);
    //CONFIGURATION_SECCTRL_1,RESERVED is Read Only
    RW_TEST_READ(CONFIGURATION_SECCTRL_1,TM_PROTECT_EN,32);
    RW_TEST_READ(CONFIGURATION_SECCTRL_1,SEC_MODE_INIT_DONE,32);
    RW_TEST_READ(CONFIGURATION_SECCTRL_1,RNG_NS_ENABLE,32);
    RW_TEST_READ(CONFIGURATION_SECCTRL_1,PKA_NS_ENABLE,32);
    RW_TEST_READ(CONFIGURATION_SECCTRL_1,AES_NS_ENABLE,32);
    RW_TEST_READ(CONFIGURATION_SECCTRL_1,DES_NS_ENABLE,32);
    RW_TEST_READ(CONFIGURATION_SECCTRL_1,SHA_NS_ENABLE,32);
    RW_TEST_READ(CONFIGURATION_SECCTRL_1,SEC_CTRL1_WR_DISABLE,32);
    RW_WRITE_PREVIOUS_VALUE(CONFIGURATION_SECCTRL_1);
    END_RW_TEST();

    BEGIN_RW_TEST(CONFIGURATION_SECCTRL_2,32);
    //RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_2,RESERVED,32);
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_2,DSP_SARAM_SEC_ENABLE,32);
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_2,DSP_DARAM_SEC_ENABLE,32);
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_2,SECURE_ELCD_ENABLE,32);
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_2,SECURE_ISRAM_ENABLE,32);
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_2,ISRAM_ERASE_START,32);
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_2,ISRAM_ERASE_DISABLE,32);
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_2,SECRAM_ERASE_START,32);
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_2,SECRAM_ERASE_DISABLE,32);
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_2,SECRAM_EXEC_DISABLE,32);
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_2,PAD_CONF_ACC_DISABLE,32);
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_2,SEC_KEYS_ACC_ENABLE,32);
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_2,WD_REG_ENABLE,32);
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_2,WD_OP_DISABLE,32);
    RW_PREPARE_WRITE(CONFIGURATION_SECCTRL_2,SEC_CTRL2_WR_DISABLE,32);
    RW_WRITE(CONFIGURATION_SECCTRL_2);
    //RW_TEST_READ(CONFIGURATION_SECCTRL_2,RESERVED,32);
    RW_TEST_READ(CONFIGURATION_SECCTRL_2,DSP_SARAM_SEC_ENABLE,32);
    RW_TEST_READ(CONFIGURATION_SECCTRL_2,DSP_DARAM_SEC_ENABLE,32);
    RW_TEST_READ(CONFIGURATION_SECCTRL_2,SECURE_ELCD_ENABLE,32);
    RW_TEST_READ(CONFIGURATION_SECCTRL_2,SECURE_ISRAM_ENABLE,32);
    RW_TEST_READ(CONFIGURATION_SECCTRL_2,ISRAM_ERASE_START,32);
    RW_TEST_READ(CONFIGURATION_SECCTRL_2,ISRAM_ERASE_DISABLE,32);
    RW_TEST_READ(CONFIGURATION_SECCTRL_2,SECRAM_ERASE_START,32);
    RW_TEST_READ(CONFIGURATION_SECCTRL_2,SECRAM_ERASE_DISABLE,32);
    RW_TEST_READ(CONFIGURATION_SECCTRL_2,SECRAM_EXEC_DISABLE,32);
    RW_TEST_READ(CONFIGURATION_SECCTRL_2,PAD_CONF_ACC_DISABLE,32);
    RW_TEST_READ(CONFIGURATION_SECCTRL_2,SEC_KEYS_ACC_ENABLE,32);
    RW_TEST_READ(CONFIGURATION_SECCTRL_2,WD_REG_ENABLE,32);
    RW_TEST_READ(CONFIGURATION_SECCTRL_2,WD_OP_DISABLE,32);
    RW_TEST_READ(CONFIGURATION_SECCTRL_2,SEC_CTRL2_WR_DISABLE,32);
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