📄 configuration.c

📁 OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器
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//===============================================================================
//            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION          
//
//   Property of Texas Instruments 
//   For  Unrestricted  Internal  Use  Only
//   Unauthorized reproduction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law 
//   as an unpublished work. 
//   Created 2000, (C) Copyright 2000 Texas Instruments.  All rights reserved.
//
//   Filename             : neptune_configuration.c
//   Date of Module Modification:5/26/04
//   Date of Generation :5/27/04
//
//===============================================================================
#include "global_types.h"
#include "configuration.h"
#include "errorcodes.h"
#include "testaccess.h"
#include "result.h"


//---------------------------------------------------------------------
// NAME        : CONFIGURATION_TestResetValue
//
// DESCRIPTION : Test the reset values of CONFIGURATION registers
//
// PARAMETERS  : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void CONFIGURATION_Test_ResetValue(void)
{
  BEGIN_RESET_MODULE();

    BEGIN_RESET_TEST(CONFIGURATION_FUNC_MUX_CTRL_0,32);
    //TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_CTRL_0,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_CTRL_0,LRU_SEL,32);
    //TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_CTRL_0,RESERVED,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_COMP_MODE_CTRL_0,32);
    //TEST_FIELD_RESET(CONFIGURATION_COMP_MODE_CTRL_0,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_COMP_MODE_CTRL_0,CONF_MUX_EN_R,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_SECCTRL_1,32);
    //TEST_FIELD_RESET(CONFIGURATION_SECCTRL_1,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_1,TM_PROTECT_EN,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_1,SEC_MODE_INIT_DONE,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_1,RNG_NS_ENABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_1,PKA_NS_ENABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_1,AES_NS_ENABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_1,DES_NS_ENABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_1,SHA_NS_ENABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_1,SEC_CTRL1_WR_DISABLE,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_SECCTRL_2,32);
    //TEST_FIELD_RESET(CONFIGURATION_SECCTRL_2,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_2,DSP_SARAM_SEC_ENABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_2,DSP_DARAM_SEC_ENABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_2,SECURE_ELCD_ENABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_2,SECURE_ISRAM_ENABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_2,ISRAM_ERASE_START,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_2,ISRAM_ERASE_DISABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_2,SECRAM_ERASE_START,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_2,SECRAM_ERASE_DISABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_2,SECRAM_EXEC_DISABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_2,PAD_CONF_ACC_DISABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_2,SEC_KEYS_ACC_ENABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_2,WD_REG_ENABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_2,WD_OP_DISABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SECCTRL_2,SEC_CTRL2_WR_DISABLE,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_SEC_TEST_CTRL,32);
    //TEST_FIELD_RESET(CONFIGURATION_SEC_TEST_CTRL,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_TEST_CTRL,OBSERVABILITY_DISABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_TEST_CTRL,DMLED_SYSTEM_EN,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_TEST_CTRL,BCM_WR_DISABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_TEST_CTRL,SEC_TEST_WR_DISABLE,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_SEC_TAP_CTRL,32);
    //TEST_FIELD_RESET(CONFIGURATION_SEC_TAP_CTRL,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_TAP_CTRL,EFUSE_TAP_ENABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_TAP_CTRL,CHIPLEVEL_TAP_ENABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_TAP_CTRL,DSP_TAP_ENABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_TAP_CTRL,MPU_TAP_ENABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_TAP_CTRL,SEC_TAP_WR_DISABLE,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_SEC_EMU_CTRL,32);
    //TEST_FIELD_RESET(CONFIGURATION_SEC_EMU_CTRL,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_EMU_CTRL,ETM_ENABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_EMU_CTRL,CTOOLS_ENABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_EMU_CTRL,MPU_DBG_ENABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_EMU_CTRL,MPU_SEC_DBG_ENABLE,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_EMU_CTRL,SEC_EMU_WR_DISABLE,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_SEC_STATUS,32);
    //TEST_FIELD_RESET(CONFIGURATION_SEC_STATUS,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_STATUS,RAM_BIST_STARTED,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_STATUS,SSM_VIOLATION,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_STATUS,WDG_RESET,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_STATUS,SEC_VIOL_RESET,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_STATUS,SEC_WDG_RESET,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_STATUS,PWR_ON_RST,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_STATUS,SECURE_RAM_ERASED,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_STATUS,ISRAM_ERASED,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_STATUS,SEC_STATUS_WR_DISABLE,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_SEC_ERROR,32);
    //TEST_FIELD_RESET(CONFIGURATION_SEC_ERROR,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_ERROR,DMA_ACC_ERROR,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_ERROR,ELCD_ACC_ERROR,32);
    //TEST_FIELD_RESET(CONFIGURATION_SEC_ERROR,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_ERROR,FRAME_BUFFER_ACC_ERROR,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_ERROR,RNG_ACC_ERROR,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_ERROR,PKA_ACC_ERROR,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_ERROR,AES_ACC_ERROR,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_ERROR,DES_ACC_ERROR,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_ERROR,SHA_ACC_ERROR,32);
    TEST_FIELD_RESET(CONFIGURATION_SEC_ERROR,SEC_ERROR_WR_DISABLE,32);
    END_RESET_TEST();

    //BEGIN_RESET_TEST(CONFIGURATION_CONF_REV,32);
    //TEST_FIELD_RESET(CONFIGURATION_CONF_REV,RESERVED,32);
    //TEST_FIELD_RESET(CONFIGURATION_CONF_REV,CONFIGURATION_REVISION_NUMBER,32);
    //END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_VOLTAGE_CTRL_0,32);
    //TEST_FIELD_RESET(CONFIGURATION_VOLTAGE_CTRL_0,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_VOLTAGE_CTRL_0,SUBLVDS_CONF_VALID_R,32);
    //TEST_FIELD_RESET(CONFIGURATION_VOLTAGE_CTRL_0,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_VOLTAGE_CTRL_0,MMC1_PWRDN,32);
    TEST_FIELD_RESET(CONFIGURATION_VOLTAGE_CTRL_0,USIM_PWRDN,32);
    TEST_FIELD_RESET(CONFIGURATION_VOLTAGE_CTRL_0,MMC_PBIAS_CTL,32);
    TEST_FIELD_RESET(CONFIGURATION_VOLTAGE_CTRL_0,USIM_PBIAS_CTL,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_USB_TRANSCEIVER_CTRL,32);
    //TEST_FIELD_RESET(CONFIGURATION_USB_TRANSCEIVER_CTRL,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_USB_TRANSCEIVER_CTRL,USB2_WRMODE,32);
    TEST_FIELD_RESET(CONFIGURATION_USB_TRANSCEIVER_CTRL,USB1_WRMODE,32);
    TEST_FIELD_RESET(CONFIGURATION_USB_TRANSCEIVER_CTRL,USB0_WRMODE,32);
    //TEST_FIELD_RESET(CONFIGURATION_USB_TRANSCEIVER_CTRL,RESERVED,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_TEST_DBG_CTRL_0,32);
    //TEST_FIELD_RESET(CONFIGURATION_TEST_DBG_CTRL_0,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_TEST_DBG_CTRL_0,CONF_RNG_TEST_OSC,32);
    TEST_FIELD_RESET(CONFIGURATION_TEST_DBG_CTRL_0,CONF_RNG_SELECT_OSC,32);
    //TEST_FIELD_RESET(CONFIGURATION_TEST_DBG_CTRL_0,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_TEST_DBG_CTRL_0,CONF_DPLL_EXT_SEL,32);
    //TEST_FIELD_RESET(CONFIGURATION_TEST_DBG_CTRL_0,RESERVED,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_MOD_CONF_CTRL_0,32);
    //TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_0,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_0,CONF_MOD_MCBSP1DIG_RF_CLKSEL,32);
    TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_0,CONF_MCBSP1_MOD,32);
    TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_0,CONF_MOD_MCBSP1_CLKS_SEL_R,32);
    TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_0,MPU_NRST_CTL,32);
    //TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_0,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_0,CAMERA_IF,32);
    TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_0,CONF_MOD_MCBSP1_CLK_SEL_R,32);
    TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_0,CONF_MOD_MMC2_CLK_SEL_R,32);
    TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_0,ISRAM_AUTO_IDLE,32);
    //TEST_FIELD_RESET(CONFIGURATION_MOD_CONF_CTRL_0,RESERVED,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_FUNC_MUX_DSP_DMA_A,32);
    //TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_DSP_DMA_A,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_DSP_DMA_A,CONF_DSP_DMA_REQ_06,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_DSP_DMA_A,CONF_DSP_DMA_REQ_05,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_DSP_DMA_A,CONF_DSP_DMA_REQ_04,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_DSP_DMA_A,CONF_DSP_DMA_REQ_03,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_DSP_DMA_A,CONF_DSP_DMA_REQ_02,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_DSP_DMA_A,CONF_DSP_DMA_REQ_01,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_FUNC_MUX_DSP_DMA_B,32);
    //TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_DSP_DMA_B,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_DSP_DMA_B,CONF_DSP_DMA_REQ_12,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_DSP_DMA_B,CONF_DSP_DMA_REQ_11,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_DSP_DMA_B,CONF_DSP_DMA_REQ_10,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_DSP_DMA_B,CONF_DSP_DMA_REQ_09,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_DSP_DMA_B,CONF_DSP_DMA_REQ_08,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_DSP_DMA_B,CONF_DSP_DMA_REQ_07,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_FUNC_MUX_DSP_DMA_C,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_FUNC_MUX_DSP_DMA_D,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_FUNC_MUX_ARM_DMA_A,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_A,CONF_ARM_DMA_REQ_05,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_A,CONF_ARM_DMA_REQ_04,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_A,CONF_ARM_DMA_REQ_03,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_A,CONF_ARM_DMA_REQ_02,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_A,CONF_ARM_DMA_REQ_01,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(CONFIGURATION_FUNC_MUX_ARM_DMA_B,32);
    //TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_B,RESERVED,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_B,CONF_ARM_DMA_REQ_10,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_B,CONF_ARM_DMA_REQ_09,32);
    TEST_FIELD_RESET(CONFIGURATION_FUNC_MUX_ARM_DMA_B,CONF_ARM_DMA_REQ_08,32);
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