uartmodem.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

{
    //enable SCR[6] (bit triggranu)
    UARTMOD_SCR_REG(UartType)|=0x40;
    //enable SCR[7] (bit triggranu)
    UARTMOD_SCR_REG(UartType)|=0x80;
    // load in FCR and TLR trig values
    UMOD_InitTlr(TxTriggerFifoLevel>>2,(RxTriggerFifoLevel>>2),UartType);
    UMOD_InitFcr(EnFifo,ClRxFifo,ClTxFifo,DmaMode,
                      (TxTriggerFifoLevel & 0x3),(RxTriggerFifoLevel & 0x3),UartType);


}


//--------------------------------
//       UMOD_InitTcr
//--------------------------------
UWORD8 UMOD_InitTcr(const UARTMOD_RxFifoTrigHalt_t   trighalt,
                       const UARTMOD_RxFifoTrigStart_t  trigstart,
                       UARTMOD_UartType_t               UartType)
{
  UWORD8 tcr_modem;
  UWORD8 efr4,mcr6,efr4old,mcr6old,lcrold;

  //Store current value LCR and set it to 0xBF to access EFR
  lcrold = UMOD_SetBfToLcr(UartType);

  //store old value EFR register and Set EFR[4]=1
  efr4old = UARTMOD_EFR_REG(UartType);
  efr4 = efr4old | 0x10;
  UARTMOD_EFR_REG(UartType) = efr4;

  mcr6old = UMOD_SetMcr6(UartType);

  UARTMOD_TCR_REG(UartType) = ( trighalt | trigstart  << 4 );
  tcr_modem       = UARTMOD_TCR_REG(UartType) ;

  //Restore old value
  UARTMOD_MCR_REG(UartType) = mcr6old;
  UARTMOD_EFR_REG(UartType) = efr4old;
  UARTMOD_LCR_REG(UartType) = lcrold;

  return tcr_modem;
}





//---------------------------------------
//          UMOD_InitTlr
//---------------------------------------
UWORD8 UMOD_InitTlr(const UARTMOD_TxFifoTrigDma_t txtrigdma,
                       const UARTMOD_RxFifoTrigDma_t rxtrigdma,
                       UARTMOD_UartType_t            UartType)
{
  UWORD8 tlr_modem;
  UWORD8 efr4,mcr6, efr4old,mcr6old,lcrold;

  //Store current value LCR and set it to 0xBF to access EFR
  lcrold = UMOD_SetBfToLcr(UartType);

  //Store old value EFR register
  efr4old = UARTMOD_EFR_REG(UartType);

  //Set bit EFR[4] =1
  efr4 = efr4old | 0x10;
  UARTMOD_EFR_REG(UartType) = efr4;

  mcr6old = UMOD_SetMcr6(UartType);

  //Set TLR
  UARTMOD_TLR_REG(UartType) = ( txtrigdma |  rxtrigdma << 4 );

  //Read TLR
  tlr_modem = UARTMOD_TLR_REG(UartType) ;

  //Restore old value
  UARTMOD_MCR_REG(UartType) = mcr6old;
  UARTMOD_EFR_REG(UartType) = efr4old;
  UARTMOD_LCR_REG(UartType) = lcrold;

  return tlr_modem;
}




//----------------------------------
//     UARTMOD_InitSSR
//----------------------------------
UWORD8 UMOD_ReadSsr(UARTMOD_UartType_t UartType)
{
  UWORD8 ssr_modem;

  ssr_modem = UARTMOD_SSR_REG(UartType) ;

  return ssr_modem;

}


//-----------------------------------
//         UMOD_ReadIir *****
//-----------------------------------
UWORD8 UMOD_ReadIir(UARTMOD_UartType_t UartType)
{
  UWORD8 lcrold, iirmodem;
//lcrold = UMOD_ClearLcr7(UartType);

  //Grant access to IIR thanks to LCR
  UMOD_CheckLcr7Is0(UartType);

  //Get IIR value
  iirmodem = UARTMOD_IIR_REG(UartType);

//UARTMOD_LCR_REG(UartType) = lcrold;
  return iirmodem;
}




//----------------------------------------------------
//           UMOD_ReadUasr
//----------------------------------------------------
UWORD8 UMOD_ReadUasr(UARTMOD_UartType_t UartType)
{
volatile UWORD8 lcrold, uasr;
 //Store current value LCR and set it to 0xBF to access UASR
 lcrold = UMOD_SetBfToLcr(UartType);
 //Get UASR register value
 uasr = UARTMOD_UASR_ST_REG(UartType);
 //Restore LCR
 UARTMOD_LCR_REG(UartType) = lcrold;

 return uasr;
}










//------------------------------------------------------
//  UMOD_TestRegisters
//------------------------------------------------------
UWORD16 UMOD_TestRegisters(UARTMOD_UartType_t UartType)
{
UWORD8 val;
UWORD16 err = RES_OK;

//--------------------------------------------------------
//  TEST THE REGISTERS VALUE ON RESET
//--------------------------------------------------------
/* UNUSED in PERSEUS
  //UIR test reset value
  val = UARTMOD_UIR_REG(UartType) & UARTMOD_UIR_REG_MASK;
  if ( val != UARTMOD_UIR_REG_RESET_VALUE )
  {
     RES_Set(UARTMOD_UIR_REG_RESET_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }
*/



  //LCR test reset value
  val = UARTMOD_LCR_REG(UartType);
  if ( val != UARTMOD_LCR_REG_RESET_VALUE )// 8
  {
     RES_Set(UARTMOD_LCR_REG_RESET_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }

  //IER test reset value
  val = UARTMOD_IER_REG(UartType);
  if ( val != UARTMOD_IER_REG_RESET_VALUE )
  {
     RES_Set(UARTMOD_IER_REG_RESET_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }

  //IIR test reset value
  val = UARTMOD_IIR_REG(UartType);
  if ( val != UARTMOD_IIR_REG_RESET_VALUE )
  {
     RES_Set(UARTMOD_IIR_REG_RESET_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }

  //SCR  test reset value
  val = UARTMOD_SCR_REG(UartType);
  if ( (val & UARTMOD_SCR_REG_MASK) != UARTMOD_SCR_REG_RESET_VALUE )
  {
     RES_Set(UARTMOD_SCR_REG_RESET_ERROR); //10
     RES_Set(val);
     err = RES_BAD;
  }


  //MCR test reset value
  val = UARTMOD_MCR_REG(UartType);
  if ( val != UARTMOD_MCR_REG_RESET_VALUE )//9
  {
     RES_Set(UARTMOD_MCR_REG_RESET_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }

  //MSR test reset value ====> Problem
  val = UARTMOD_MSR_REG(UartType) & UARTMOD_MSR_REG_MASK;
  if ( val != UARTMOD_MSR_REG_RESET_VALUE )
  {
     RES_Set(UARTMOD_MSR_REG_RESET_ERROR);//b
     RES_Set(val);
     err = RES_BAD;
  }

  //MDR1  test reset value
  val = UARTMOD_MDR1_REG(UartType) & UARTMOD_MDR1_REG_MASK;
  if ( val != UARTMOD_MDR1_REG_RESET_VALUE )
  {
     RES_Set(UARTMOD_MDR1_REG_RESET_ERROR);//e
     RES_Set(val);
     err = RES_BAD;
  }

  //SSR  test reset value
  val = UARTMOD_SSR_REG(UartType);
  if ( val != UARTMOD_SSR_REG_RESET_VALUE ) //11
  {
     RES_Set(UARTMOD_SSR_REG_RESET_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }


  //RHR, THR, DLL, DLH are undefined on reset



  //EFR test reset value
  UARTMOD_LCR_REG(UartType)=0xBF; //set lcr register to 0xBF for access to EFR register
  val = UARTMOD_EFR_REG(UartType);
  if ( val != UARTMOD_EFR_REG_RESET_VALUE )
  {
     RES_Set(UARTMOD_EFR_REG_RESET_ERROR); // 7
     RES_Set(val);
     err = RES_BAD;
  }
  UARTMOD_LCR_REG(UartType)=0x0; //reset lcr register



// =========> Problem
// set EFR[4]=1 and MCR[6]=1 for access to TCR and TLR
  UARTMOD_EFR_REG(UartType) |= 0x10; // set EFR[4]=1
  UARTMOD_MCR_REG(UartType) |= 0x40; // set MCR[6]=1
  //TLR  test reset value
  val = UARTMOD_TLR_REG(UartType);
  if ( val != UARTMOD_TLR_REG_RESET_VALUE )
  {
     RES_Set(UARTMOD_TLR_REG_RESET_ERROR);//d
     RES_Set(val);
     err = RES_BAD;
  }
  val = UARTMOD_TCR_REG(UartType);
  if ( val != UARTMOD_TCR_REG_RESET_VALUE )
  {
     RES_Set(UARTMOD_TCR_REG_RESET_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }

  UARTMOD_EFR_REG(UartType) &= ~0x10; // reset EFR[4]=1
  UARTMOD_MCR_REG(UartType) &= ~0x40; // reset MCR[6]=1



  //UASR  test reset value
  UARTMOD_LCR_REG(UartType)=0x80; //set lcr[7] =1 for access to UASR register
  val = UARTMOD_UASR_ST_REG(UartType);
  if ( val != UARTMOD_UASR_REG_RESET_VALUE )
  {
     RES_Set(UARTMOD_UASR_REG_RESET_ERROR);//f
     RES_Set(val);
     err = RES_BAD;
  }
  UARTMOD_LCR_REG(UartType)=0x0; //reset lcr register


//--------------------------------------------------------
//  TEST THE ACCESS TO REGISTERS WRITE PLUS READ-BACK
//--------------------------------------------------------

  //UIR test access
  UARTMOD_UIR_REG(UartType) = 0x03;
  val = UARTMOD_UIR_REG(UartType) & UARTMOD_UIR_REG_MASK;
  if ( val != 0x03 )
  {
     RES_Set(UARTMOD_UIR_ACCESS_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }

  //RHR, THR, DLL, DLH are undefined on reset



  //SCR  W/R test
  UARTMOD_SCR_REG(UartType) = 0x08;
  // read back
  val = UARTMOD_SCR_REG(UartType);
  if ( (val & UARTMOD_SCR_REG_MASK) != 0x08 )
  {
     RES_Set(UARTMOD_SCR_REG_ACCESS_ERROR); //10
     RES_Set(val);
     err = RES_BAD;
  }

  //LCR  W/R test
  UARTMOD_LCR_REG(UartType) = 0x03;
  val = UARTMOD_LCR_REG(UartType);
  // read back
  if ( val != 0x03 )// 8
  {
     RES_Set(UARTMOD_LCR_REG_ACCESS_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }

  //IER test access
  // set EFR[4]=1 for write in IER
  UARTMOD_EFR_REG(UartType) |= 0x10; // set EFR[4]=1

  UARTMOD_IER_REG(UartType) = 0x34;
  // read back
  val = UARTMOD_IER_REG(UartType) ;
  if ( val != 0x034 )
  {
     RES_Set(UARTMOD_IER_REG_ACCESS_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }
  UARTMOD_EFR_REG(UartType) &= ~0x10; // reset EFR[4]=1



  //EFR test access
  UARTMOD_LCR_REG(UartType)=0xBF; //set lcr register to 0xBF for access to EFR register
  UARTMOD_EFR_REG(UartType) = 0x66;
  val = UARTMOD_EFR_REG(UartType) ;
  if ( val != 0x66 )
  {
     RES_Set(UARTMOD_EFR_REG_ACCESS_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }
  UARTMOD_LCR_REG(UartType)=0x0; // reset lcr register




  //MCR test access
  UARTMOD_EFR_REG(UartType) |= 0x10; // set EFR[4]=1

  UARTMOD_MCR_REG(UartType) = 0x22;
  val = UARTMOD_MCR_REG(UartType) ;
  if ( val != 0x22 )
  {
     RES_Set(UARTMOD_MCR_REG_ACCESS_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }
  UARTMOD_EFR_REG(UartType) &= ~0x10; // reset EFR[4]=1

  //XON1/ADDR1 undefined on reset


  //XON2/ADDR2 undefined on reset

  //MSR is readable only


  UARTMOD_EFR_REG(UartType) |= 0x10; // set EFR[4]=1
  UARTMOD_MCR_REG(UartType) |= 0x40; // set MCR[6]=1
  //TCR test access
  UARTMOD_TCR_REG(UartType) = 0x44;
  val = UARTMOD_TCR_REG(UartType);
  if ( val != 0x44 )
  {
     RES_Set(UARTMOD_TCR_REG_ACCESS_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }

  //XOFF1, XOFF2, SPR   are undefined on reset

  //TLR  test access
  UARTMOD_TLR_REG(UartType) = 0x88;
  val = UARTMOD_TLR_REG(UartType);
  if ( val != 0x88 )
  {
     RES_Set(UARTMOD_TLR_REG_ACCESS_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }
  UARTMOD_EFR_REG(UartType) &= ~0x10; // reset EFR[4]=1
  UARTMOD_MCR_REG(UartType) &= ~0x40; // reset MCR[6]=1


  //MDR1  test access
  UARTMOD_MDR1_REG(UartType) = 0x2E;
  val = UARTMOD_MDR1_REG(UartType) & UARTMOD_MDR1_REG_MASK;
  if ( val != 0x2E )
  {
     RES_Set(UARTMOD_MDR1_REG_ACCESS_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }


  return err;
}


//----------------------------------------------------
//  UMOD_IsTransmitAndHoldRegNotEmpty          -
//----------------------------------------------------
UWORD8 UMOD_IsTransmitAndHoldRegNotEmpty(UARTMOD_UartType_t UartType)
{
UWORD8 not_empty;
UWORD8 current_lcr = UARTMOD_LCR_REG(UartType);
  //set LCR[7]=0 to access LSR Register
  UARTMOD_LCR_REG(UartType) &= 0x7F;

  not_empty = ! ( (UARTMOD_LSR_REG(UartType) & UARTMOD_LSR_EMPTY1) >> 6 );

  //Restore LCR
  UARTMOD_LCR_REG(UartType) = current_lcr;
  return not_empty;
}


//---------------------------------------
//  UMOD_RxFifoIsNotEmpty            -
//---------------------------------------
boolean_t UMOD_RxFifoIsNotEmpty(UARTMOD_UartType_t UartType)
{
  return (boolean_t) (UARTMOD_LSR_REG(UartType) & 0x01 );
}

//  UMOD_TxFifoIsFull            -
//---------------------------------------
boolean_t UMOD_TxFifoIsFull(UARTMOD_UartType_t UartType)
{
  return (boolean_t) (UARTMOD_SSR_REG(UartType) & UARTMOD_SSR_TXFIFOFULL_NUMB );
}