📄 gdmatest_omap32.c
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//=====================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments -- For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited
// This product is protected under copyright law and trade secret law as
// an unpublished work.Created 2001,(C) Copyright 2001 Texas Instruments.
// All rights reserved.
//=====================================================================
#include "test.h"
#include "gdmatest.h"
#include "gdma_omap32.h"
#include "gdmatest_omap32.h"
#include "result.h"
extern DMA_SYSTEM_STRUCT_OMAP32 SystemDma_omap32;
//-------------------------------------------------------------------------------
// NAME : DMAT_SpyWriteFailResults_OMAP32
//
// DESCRIPTION : Verify the data in the destination using the same algorithm
// than for the source
//
// PARAMETERS : ChannelNumber DMA_CHANNEL_0
// DMA_CHANNEL_1
// DMA_CHANNEL_2
// DMA_CHANNEL_3
// DMA_CHANNEL_4
// DMA_CHANNEL_5
// DMA_CHANNEL_6
// DMA_CHANNEL_7
// DMA_CHANNEL_8
// DMA_CHANNEL_9
// DMA_CHANNEL_10
// DMA_CHANNEL_11
// DMA_CHANNEL_12
// DMA_CHANNEL_13
// DMA_CHANNEL_14
// DMA_CHANNEL_15
// DMA_CHANNEL_LCD
// i Loop counter value
// FailData Memory read data to write into spy
// ExpectedData Generated pattern data expected from memory.
//
//
// RETURN VALUE : none
//
//--------------------------------------------------------------------------------
BOOL DMAT_SpyWriteFailResults_OMAP32( UWORD16 ChannelNumber, UWORD16 i, UWORD16 FailData,
UWORD16 ExpectedData)
{
CHANNEL_DESCRIPTOR_OMAP32* Chptr;
Chptr=&(SystemDma_omap32.DmaChannel[ChannelNumber]);
RES_Set(START_ARRAY_DATA);
RES_Set(i);
RES_Set(ExpectedData);
RES_Set(FailData);
RES_Set(END_ARRAY_DATA);
switch(Chptr->DestAddressMode)
{
case DMA_ADD_CONSTANT :
{
RES_Set(DMA_VERIF_CONSTANT_ERR);
break;
}
case DMA_ADD_POSTINC :
{
RES_Set(DMA_VERIF_POSTINC_ERR);
break;
}
case DMA_ADD_SINGLE_INDEX :
{
RES_Set(DMA_VERIF_SINGLEADD_ERR);
break;
}
case DMA_ADD_DOUBINDEX :
{
RES_Set(DMA_VERIF_DOUBLEADD_ERR);
break;
}
default:
{
RES_Set(RESULT_SEPARATOR);
RES_GetFinal2();
RES_StopVhdl();
break;
}
}
RES_Set(RESULT_SEPARATOR);
RES_GetFinal2();
RES_StopVhdl();
return(True);
}
//-------------------------------------------------------------------------------
// NAME : DMAT_InitializeOrVerifyData_OMAP32
//
// DESCRIPTION : Either initialize or Verify the data involved in the DMA transfer.
//
// PARAMETERS : ChannelNumber DMA_CHANNEL_0
// DMA_CHANNEL_1
// DMA_CHANNEL_2
// DMA_CHANNEL_3
// DMA_CHANNEL_4
// DMA_CHANNEL_5
// DMA_CHANNEL_6
// DMA_CHANNEL_7
// DMA_CHANNEL_8
// DMA_CHANNEL_9
// DMA_CHANNEL_10
// DMA_CHANNEL_11
// DMA_CHANNEL_12
// DMA_CHANNEL_13
// DMA_CHANNEL_14
// DMA_CHANNEL_15
// DMA_CHANNEL_LCD
//
// MemMode INITIALIZE_MEM
// VERIFY_MEM
//
//
// RETURN VALUE : IS_OK or NOT_OK if something fail
//
//--------------------------------------------------------------------------------
BOOL DMAT_InitializeOrVerifyData_OMAP32( UWORD16 ChannelNumber, UWORD16 MemMode )
{
UWORD32 BlockSize, i, rtn_status, AddressMode, Address;
CHANNEL_DESCRIPTOR_OMAP32* Chptr;
UWORD8 AddressAlign;
rtn_status = IS_OK;
Chptr=&(SystemDma_omap32.DmaChannel[ChannelNumber]);
if (ChannelNumber != DMA_CHANNEL_LCD_OMAP32)
{
BlockSize = Chptr->EltNumber * Chptr->FrameNumber;
if (MemMode == INITIALIZE_MEM)
{
AddressMode = (Chptr->SrcAddressMode);
Address = (Chptr->SrcAdd);
AddressAlign = (Chptr->SrcAdd) % 4;
}
else
{
AddressMode = (Chptr->DestAddressMode);
Address = (Chptr->DestAdd);
AddressAlign = (Chptr->DestAdd) % 4;
}
switch(AddressMode)
{
//--------------------------------------------------------------------------------
case DMA_ADD_CONSTANT:
{
switch(MemMode)
{
case INITIALIZE_MEM:
{
switch(Chptr->TypeSize)
{
case DMA_TYPE_32_BITS:
{
switch(AddressAlign)
{
case 0x00: // Then 32-bit aligned
{
UWORD32* MemPtr;
i = BlockSize;
MemPtr = (UWORD32*)Address;
*MemPtr = DMAT_GeneratePattern(Chptr->Pattern,i);
break;
}
case 0x02: // Then 16-bit aligned
{
UWORD16* MemPtr;
i = BlockSize;
MemPtr = (UWORD16*)Address;
*MemPtr++ = (UWORD16)DMAT_GeneratePattern(Chptr->Pattern,i);
*MemPtr = (UWORD16)((DMAT_GeneratePattern(Chptr->Pattern,i))>>16);
break;
}
case 0x01: // Then 8-bit aligned
{
UWORD8* MemPtr;
i = BlockSize;
MemPtr = (UWORD8*)Address;
*MemPtr++ = (UWORD8)DMAT_GeneratePattern(Chptr->Pattern,i);
*MemPtr++ = (UWORD8)((DMAT_GeneratePattern(Chptr->Pattern,i))>>8);
*MemPtr++ = (UWORD8)((DMAT_GeneratePattern(Chptr->Pattern,i))>>16);
*MemPtr = (UWORD8)((DMAT_GeneratePattern(Chptr->Pattern,i))>>24);
break;
}
} // End of switch(SrcAddressAlign)
break;
} // End of case DMA_TYPE_32_BITS
case DMA_TYPE_16_BITS:
{
if (AddressAlign == 0x01) // Then 8-bit aligned
{
UWORD8* MemPtr;
i = BlockSize;
MemPtr = (UWORD8*)Address;
*MemPtr++ = (UWORD8)DMAT_GeneratePattern(Chptr->Pattern,i);
*MemPtr = (UWORD8)((DMAT_GeneratePattern(Chptr->Pattern,i))>>8);
}
else
{
UWORD16* MemPtr;
i = BlockSize;
MemPtr = (UWORD16*)Address;
*MemPtr++ = (UWORD16)DMAT_GeneratePattern(Chptr->Pattern,i);
}
break;
} // End of case DMA_TYPE_16_BITS
case DMA_TYPE_8_BITS:
{
UWORD8* MemPtr;
i = BlockSize;
MemPtr = (UWORD8*)Address;
*MemPtr = (UWORD8)DMAT_GeneratePattern(Chptr->Pattern,i);
break;
} // End of case DMA_TYPE_8_BITS
} // End of switch(Chptr->TypeSize)
break;
} // End of case : INITIALIZE_MEM
case VERIFY_MEM:
{
switch(Chptr->TypeSize)
{
case DMA_TYPE_32_BITS:
{
switch(AddressAlign)
{
case 0x00: // Then 32-bit aligned
{
UWORD32* MemPtr;
i = BlockSize;
MemPtr = (UWORD32*)Address;
if (*MemPtr != DMAT_GeneratePattern(Chptr->Pattern,i))
{
DMAT_SpyWriteFailResults( ChannelNumber, i, (0x0000FFFF & (*MemPtr)),
(0x0000FFFF & (DMAT_GeneratePattern(Chptr->Pattern,i))));
rtn_status = NOT_OK;
}
break;
}
case 0x02: // Then 16-bit aligned
{
UWORD16* MemPtr;
i = BlockSize;
MemPtr = (UWORD16*)Address;
if ((UWORD16)(*MemPtr++) != (UWORD16)DMAT_GeneratePattern(Chptr->Pattern,i))
{
DMAT_SpyWriteFailResults( ChannelNumber, i, (0x0000FFFF & (*MemPtr)),
(0x0000FFFF & (DMAT_GeneratePattern(Chptr->Pattern,i))));
rtn_status = NOT_OK;
break;
}
else if ((UWORD16)(*MemPtr) != (UWORD16)(DMAT_GeneratePattern(Chptr->Pattern,i)>>16))
{
DMAT_SpyWriteFailResults( ChannelNumber, i, (0x0000FFFF & (*MemPtr)),
(0x0000FFFF & ((DMAT_GeneratePattern(Chptr->Pattern,i))>>16)));
rtn_status = NOT_OK;
break;
}
break;
}
case 0x01: // Then 8-bit aligned
{
UWORD8* MemPtr;
i = BlockSize;
MemPtr = (UWORD8*)Address;
if ((UWORD8)(*MemPtr++) != (UWORD8)DMAT_GeneratePattern(Chptr->Pattern,i))
{
DMAT_SpyWriteFailResults( ChannelNumber, i, (0x0000FFFF & (*MemPtr)),
(0x0000FFFF & (DMAT_GeneratePattern(Chptr->Pattern,i))));
rtn_status = NOT_OK;
break;
}
else if ((UWORD8)(*MemPtr++) != (UWORD8)(DMAT_GeneratePattern(Chptr->Pattern,i)>>8))
{
DMAT_SpyWriteFailResults( ChannelNumber, i, (0x0000FFFF & (*MemPtr)),
(0x0000FFFF & ((DMAT_GeneratePattern(Chptr->Pattern,i))>>8)));
rtn_status = NOT_OK;
break;
}
else if ((UWORD8)(*MemPtr++) != (UWORD8)(DMAT_GeneratePattern(Chptr->Pattern,i)>>16))
{
DMAT_SpyWriteFailResults( ChannelNumber, i, (0x0000FFFF & (*MemPtr)),
(0x0000FFFF & ((DMAT_GeneratePattern(Chptr->Pattern,i))>>16)));
rtn_status = NOT_OK;
break;
}
else if ((UWORD8)(*MemPtr) != (UWORD8)(DMAT_GeneratePattern(Chptr->Pattern,i)>>24))
{
DMAT_SpyWriteFailResults( ChannelNumber, i, (0x0000FFFF & (*MemPtr)),
(0x0000FFFF & ((DMAT_GeneratePattern(Chptr->Pattern,i))>>24)));
rtn_status = NOT_OK;
break;
}
break;
}
} // End of switch(SrcAddressAlign)
break;
} // End of case DMA_TYPE_32_BITS
case DMA_TYPE_16_BITS:
{
if (AddressAlign == 0x01) // Then 8-bit aligned
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