intvecs_sdram.asm

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

EMIFS_CS_CFG2_ADDR              .word   0xFFFECC18
EMIFS_CS_ACFG2_ADDR             .word   0xFFFECC58
EMIFS_CS_CFG3_ADDR              .word   0xFFFECC1C
EMIFS_CS_ACFG3_ADDR             .word   0xFFFECC5C

; no clk div/no retiming/9 rw wait state/RDMODE 0 (async)/MUXDED 16 bits/Ref clk= TCK(env 102.1MHZ/9,8ns)
; insert 5 wait states to respect slowest norflash (cs3) rw timing >= 85 ns
;mode1_emifs_cfg_val             .word   0xFFC0F990
; BT mode=0/ADVHOLD=1/OEHOLD=0/OESETUP=3
; increase adv to respect slowest norflash (cs3) adv timing >= 10ns
;mode1_emifs_adv_cfg_val         .word   0x00000103

emifs_cfg_val                   .word   0x00004078 ; 7 RWS, 0 WWS, 4 PWS. Fclk div=1



ARM_SYSST_reg                   .word   0xFFFECE18
; bit 12 allows to select the synchronous scalable mode
ARM_SYSST_val                   .word   0x00001000

;
; ARM CKCTL : sets ARM clock to be output of the DPLL1,
; ARM inth and TC run at ARM/2. DSP runs at ARM frequency
;
ARM_CKCTL_reg                   .word   0xFFFECE00
ARM_CKCTL_val                   .word   0x00005101
ARM_IDLECT2_ADDR	        .word   0xFFFECE08
ARM_IDLECT2_VAL		        .word   0x0006
ARM_RSTCT2_ADDR	        	.word   0xFFFECE14
ARM_RSTCT2_VAL		        .word   0x0001

AddrDpll                        .word   0xFFFECF00
pllratio                         .word   0x00002A10   ;; mult 20, div 1 -> 13.0 * 20   = 260.0 MHz
;mode1_pllratio                  .word   0x00002BB0   ;; mult 23, div 2 -> 19.2 * 10.5 = 220.8 MHz
privilege_stack_base            .word   0x20000000

;=========================================================================================
; Some SWI handlers used in C code
;=========================================================================================
	.text
	.state32
;
; INT_Swi(unsigned stack, unsigned stackSize)
;                  R0              R1
;
; Enable exception and set up a stack
; Works only if called from 16-bit (THUMB) mode
;
;
INT_Swi:
        LDRH    r4, [LR, #-2]     ; retrieve SWI parameter
	AND	r4, r4, #0xFF	  ; keep the argument only

	CMP     r4, #0xFA
        BEQ     SetSupervisor

        CMP     r4, #0xFB
        BEQ     SetUser

	CMP     r4, #0xFC
        BEQ     EnableFIQ

	CMP     r4, #0xFD
        BEQ     EnableIRQ

	CMP	r4, #0xF5
	BEQ	Set_SVC_Stack

	CMP	r4, #0xF4
	BEQ	Set_AbortD_Stack

	CMP	r4, #0xF0
	BEQ	SetIRQBit

	CMP	r4, #0xF1
	BEQ	ClearIRQBit

	CMP	r4, #0xF2
	BEQ	SetFIQBit

	CMP	r4, #0xF3
	BEQ	ClearFIQBit

	B       ExitSwi           ; not handled


SetSupervisor:
	MRS	r7, SPSR	  ; Take a copy of Program Status Register
	BIC	r7,r7,#MODE_MASK  ; Clear the mode bits
	ORR	r7,r7,#SUP_MODE	  ; Set Supervisor Mode
	MSR	SPSR, r7	  ; Write back the modified SPSR
	B       ExitSwi           ; not handled

SetUser:
	MRS	r7, SPSR		; Get copy of Program Status Register
	BIC	r7, r7, #MODE_MASK	; Clear mode bits
	ORR	r7, r7, #USR_MODE	; Set User Mode
	MSR	SPSR, r7		; Write back modified SPSR
	B       ExitSwi			; not handled

EnableIRQ:
        MOV     r5, #IRQ_MODE
        MOV     r6, #IRQ_MASK
        B       DoIt

EnableFIQ:
        MOV     r5, #FIQ_MODE
        MOV     r6, #FIQ_MASK
	B       DoIt

Set_SVC_Stack:
	;STACK MANIPULATION
        MOV     SP, r0            ; stack address
	MOV	r1,r1,lsl #2      ; convertion from word size to byte size
        ADD     SP, r1, SP        ; add size to get initial SP
	B	ExitSwi

Set_AbortD_Stack:
	MRS	r2, CPSR
	BIC	r2, r2, #MODE_MASK
	ORR	r2, r2, #ABORT_MODE
	MSR	CPSR, r2						; set abort mode
	;STACK MANIPULATION
        MOV     SP, r0            ; stack address
	MOV	r1,r1,lsl #2      ; convertion from word size to byte size
        ADD     SP, r1, SP        ; add size to get initial SP
	BIC	r2, r2, #MODE_MASK
	ORR	r2, r2, #SUP_MODE
	MSR	CPSR, r2						; restore supervisor mode
	B	ExitSwi

SetIRQBit:
	MOV     r5, #IRQ_MASK
        MOV     r6, #SET_BIT
	B       SetClearFIQIRQ

ClearIRQBit:
	MOV     r5, #IRQ_MASK
        MOV     r6, #CLEAR_BIT
	B       SetClearFIQIRQ

SetFIQBit:
	MOV     r5, #FIQ_MASK
        MOV     r6, #SET_BIT
	B       SetClearFIQIRQ

ClearFIQBit:
	MOV     r5, #FIQ_MASK
        MOV     r6, #CLEAR_BIT
	B       SetClearFIQIRQ

SetClearFIQIRQ:
	MRS     r7, SPSR          ; read saved PSR
	BIC     r7, r7, r5        ; clear FIQ or IRQ bit of saved PSR
	CMP	r6, #CLEAR_BIT    ; if equal to #CLEAR_BIT
	BEQ	STORE_SPSR        ; do not set any bit of saved PSR
        ORR     r7, r7, r5        ; set FIQ or IRQ bit of saved PSR
STORE_SPSR:
        MSR     SPSR, r7          ; store saved PSR to set or clear FIQ or IRQ bit
	B	ExitSwi

DoIt:
	;Set FIQ or IRQ mode before reset I/F bit to prevent interruption
        MRS     r4, CPSR          ; read current PSR
        BIC     r4,r4,#MODE_MASK  ; remove all mode bits
        ORR     r4,r4,r5          ; set desired mode
        MSR     CPSR, r4          ; set current mode to disable FIQ or IRQ catch
	;STACK MANIPULATION
        MOV     SP, r0            ; stack address
	MOV	r1,r1,lsl #2      ; convertion from word size to byte size
        ADD     SP, r1, SP        ; add size to get initial SP

	BIC     r4,r4,#MODE_MASK  ; remove all mode bits
        ORR     r4,r4,#SUP_MODE
        MSR     CPSR, r4          ; reset supervisor mode

        MRS     r4,SPSR           ; read stored status reg
        BIC     r4,r4,r6          ; Enable exception
        MSR     SPSR,r4           ; set stored status reg

ExitSwi:
	MOVS    PC, R14           ; return from SWI

	.state16
$INT_SetSupervisor
	MOV	r3, LR
        SWI     #0xFA         ; 0xFA : Enable INT_Swi
        MOV     PC, r3

$INT_SetUser:
	MOV	r3, LR
        SWI     #0xFB        ; 0xFB : Enable INT_Swi
	MOV     PC, r3

;
; INT_EnableIRQ(unsigned stack, unsigned stackSize)
;                    R0              R1
;
; Enable IRQ and set up a stack - perform SWI to switch to supervisor mode
;
$INT_EnableIRQ:
	MOV	r3, LR
        SWI     #0xFD                   ; 0xFD : Enable IRQ
        MOV     PC, r3

;
; INT_EnableFIQ(unsigned stack, unsigned stackSize)
;                  R0              R1
;
; Enable FIQ and set up a stack - perform SWI to switch to supervisor mode
;
$INT_EnableFIQ:
	MOV	r3, LR
        SWI     #0xFC                   ; 0xFE : Enable FIQ
        MOV     PC, r3

;
; INT_Set_SVC_Stack(unsigned stack, unsigned stackSize)
;                      R0              R1
;
; Set up a stack for supervisor mode - perform SWI to switch to supervisor mode
;
$INT_Set_SVC_Stack:
	MOV	r3, LR
        SWI     #0xF5                   ; 0xF5 : Set Supervisor Stack
        MOV     PC, r3

	;
; INT_Set_SVC_Stack(unsigned stack, unsigned stackSize)
;                      R0              R1
;
; Set up a stack for supervisor mode - perform SWI to switch to supervisor mode
;
$INT_Set_AbortD_Stack:
	MOV	r3, LR
        SWI     #0xF4                   ; 0xF4 : Set AbortD Stack
        MOV     PC, r3

;
; INT_SetIRQBit
;
; Set IRQ bit of PSR (Program Status Register)
; (Disable IRQ)
;
$INT_SetIRQBit:
	MOV	r3, LR
        SWI     #0xF0                   ; 0xF0 : Set IRQ Bit of PSR
        MOV     PC, r3

;
; INT_ClearIRQBit
;
; Clear IRQ bit of PSR (Program Status Register)
; (Enable IRQ)
;
$INT_ClearIRQBit:
	MOV	r3, LR
        SWI     #0xF1                   ; 0xF1 : Clear IRQ Bit of PSR
        MOV     PC, r3

;
; INT_SetFIQBit
;
; Set FIQ bit of PSR (Program Status Register)
; (Disable FIQ)
;
$INT_SetFIQBit:
	MOV	r3, LR
        SWI     #0xF2                   ; 0xF2 : Set FIQ Bit of PSR
        MOV     PC, r3

;
; INT_ClearFIQBit
;
; Clear FIQ bit of PSR (Program Status Register)
; (Enable FIQ)
;
$INT_ClearFIQBit:
	MOV	r3, LR
        SWI     #0xF3                   ; 0xF3 : Clear FIQ Bit of PSR
        MOV     PC, r3


        .end                    ; Terminate assembly