intvecs_sdram.asm

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

;******************************************************************************
;            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
;
;   Property of Texas Instruments
;   For  Unrestricted  Internal  Use  Only
;   Unauthorized reproduction and/or distribution is strictly prohibited.
;   This product is protected under copyright law and trade secret law
;   as an unpublished work.
;
;   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.
;
;
;*******************************************************************************


	.state32
        .global _reset
        .global _c_int00
        .global _EX_AbortD
        .global _EX_Irq
        .global _EX_Fiq
        .global INT_Swi

	.global $INT_SetSupervisor
	.global $INT_SetUser
        .global $INT_EnableIRQ
        .global $INT_EnableFIQ
	.global $INT_SetIRQBit
        .global $INT_ClearIRQBit
	.global $INT_SetFIQBit
        .global $INT_ClearFIQBit
	.global $INT_Set_SVC_Stack
	.global $INT_Set_AbortD_Stack

        .sect ".intvecs"

_reset	LDR	pc, initBasicCall       ;  RESET INTERRUPT
undef:	B       undef           	;  UNDEFINED INSTRUCTION INTERRUPT
        LDR     pc, INT_SwiCall         ;  SOFTWARE INTERRUPT
abort1: B       abort1                  ;  ABORT (PREFETCH) INTERRUPT
	LDR     pc, _EX_AbortDCall      ;  ABORT (DATA) INTERRUPT
reserv: B	reserv                  ;  RESERVED
        LDR	pc, _EX_IrqCall         ;  IRQ INTERRUPT
        LDR	pc, _EX_FiqCall         ;  FIQ INTERRUPT

IRQ_MASK        .equ     0x80           ; IRQ mask value
FIQ_MASK        .equ     0x40           ; FIQ mask value
MODE_MASK       .equ     0x1F           ; Processor Mode Mask

FIQ_MODE        .equ     0x11           ; Fast Interrupt Mode (FIQ)
IRQ_MODE        .equ     0x12           ; Interrupt Mode (IRQ)
SUP_MODE        .equ     0x13           ; Supervisor Mode
USR_MODE        .equ     0x10           ; User Mode
ABORT_MODE      .equ     0x17           ; Abort Mode
SYS_MODE        .equ     0x1F           ; System mode

CLEAR_BIT       .equ     0x00           ; Clear Bit
SET_BIT         .equ     0x01           ; Set Bit

initBasicCall	.word initBasic

INT_SwiCall	.word INT_Swi

_EX_AbortDCall	.word _EX_AbortD

_EX_IrqCall	.word _EX_Irq

_EX_FiqCall	.word _EX_Fiq

       .sect ".boot"

; Basic Initializations

initBasic:
        ;; -------Flush Instruction cache-------
        ;; --------------------------------------
	;;MOV     r1,#0
	;;MCR     p15, #0, r1, c7, c5  ; Flush Instruction Cache

        ;; -------Enable Instruction cache-------
        ;; --------------------------------------
        ;;MRC	  p15, #0, R1, C1, C0
        ;;ORR     R1, R1, #0x1000
        ;;MCR     P15, #0, R1, C1, C0
        ;; --------------------------------------

; Set the synchronous scalable mode
;
        LDR     r0,ARM_SYSST_reg
        LDR     r2,ARM_SYSST_val
        STR     r2,[r0]
;
; Set clock divider : ARM and DSP run at DPLL freq, TC runs at DPLL/2
;
        LDR     r0,ARM_CKCTL_reg
        LDR     r2,ARM_CKCTL_val
        STR     r2,[r0]
;
; Sets DPLL ratio
;
	MOV   r4, #1
	LDR   r2, pllratio

        LDR   r0, AddrDpll
        STR   r2, [r0]

wait_dpll_lock:
	LDR   r2, [r0]
	TST   r2, r4
	BEQ   wait_dpll_lock


;emiff_setup:
;	LDR   r0, EMIFF_SDRAM_OPERATION_ADDR  ; Setup DDR type
;	MOV   r2, #0x00000007                 ; DDR SDRAM K4X28163 configuration  (mobile DDR, HPHB mode)
;	STR   r2, [r0]
;
;	LDR   r5, EMIFF_SDRAM_CONFIG_ADDR
;        LDR   r2, emiff_cfg_val         ; Setup DDR cfg
;	STR   r2, [r5]
;
;	LDR   r6, EMIFF_SDRAM_MANUAL_CMD_ADDR ; Manual init sequence
;	MOV   r2, #0x00000007                 ; Set CKE high command
;	STR   r2, [r6]
;	MOV   r2, #0x00000000                 ; NOP          command
;	STR   r2, [r6]
;
;	MOV   r2, #0x0100                     ; a little loop
;wait_loop:
;        SUBS  r2, r2, #1
;	BNE   wait_loop
;
;	MOV   r2, #0x00000001                 ; Precharge    command
;	STR   r2, [r6]
;	MOV   r2, #0x00000002                 ; Auto-refresh command (x2)
;	STR   r2, [r6]
;	STR   r2, [r6]
;
;	LDR   r6, EMIFF_SDRAM_MRS_NEW_ADDR    ; MRS
;	MOV   r2, #0x00000033                 ;
;	STR   r2, [r6]
;
;	LDR   r6, EMIFF_SDRAM_EMRS1_ADDR      ; EMRS1
;	MOV   r2, #0                          ; Self refresh on all banks
;	STR   r2, [r6]
;
;	MOV   r2, #6
;	LDR   r6, EMIFF_DLL_URD_CONTROL_ADDR
;	STR   r2, [r6]
;	LDR   r6, EMIFF_DLL_LRD_CONTROL_ADDR
;	STR   r2, [r6]
;	LDR   r6, EMIFF_DLL_WRT_CONTROL_ADDR
;	STR   r2, [r6]
;	B     emifs_setup

emiff_setup:
      	LDR	r0, EMIFF_SDRAM_CONFIG_ADDR
	LDR	r2, emiff_cfg_val
	STR	r2, [r0]

	LDR	r0, EMIFF_SDRAM_MRS_ADDR
	LDR	r2, ValueEmifFastMRS
	STR	r2, [r0]

emifs_setup:
   LDR     r2, emifs_cfg_val
   LDR     r0, EMIFS_CS_CFG3_ADDR
	STR     r2, [r0]
   B       stack_setup

stack_setup:
	LDR     r0, privilege_stack_base
	MOV     r1, #0x50
;
; SWI handler needs to be called in thumb mode, so that the SWI function
; can be directly called from C code. We switch to thumb mode
;
	ADR	r2, to_thumb + 1
	BX	r2
	.state16
to_thumb:
;
; Sets up SVC stack
;
	SWI     #0xF5
;
; Sets up DATA ABORT stack
;
; r1 contains size of stack (in words = 0x50)
	MOV     r1, #0x50
	LSL	r2, r1, #2
; r0 contains stack base address (= previous base address + size*4)
	ADD	r0, r2
	SWI	#0xF4
;
; Sets up FIQ stack and enables FIQ
;
	MOV     r1, #0x50
	LSL	r2, r1, #2
	ADD	r0, r2
	SWI     #0xFC
;
; Sets up IRQ stack and enables IRQ
;
	MOV     r1, #0x50
	LSL	r2, r1, #2
	ADD	r0, r2
	SWI     #0xFD
;
; Back to ARM mode
        ADR r0, to_arm_code         ; Switch to ARM mode
        BX  r0

	.state32
to_arm_code:
;
; Enables ARMPERCK and ARMXORCK
;
	LDR r0, ARM_IDLECT2_ADDR
	LDR r1, ARM_IDLECT2_VAL
	LDR r2, [r0]
	ORR  r2, r2, r1
	STR r2, [r0]
;
; Releases ARMPERRST
;
	LDR r0, ARM_RSTCT2_ADDR
	LDR r1, ARM_RSTCT2_VAL
	LDR r2, [r0]
	ORR  r2, r2, r1
	STR r2, [r0]
;
; Sets up
; Initialize ARM925T internal registers.
	MOV	r0, #0
	MOV	r1, #0
	MOV	r2, #0
	MOV	r3, #0
	MOV	r4, #0
	MOV	r5, #0
	MOV	r6, #0
	MOV	r7, #0
	MOV	r8, #0
	MOV	r9, #0
	MOV	r10, #0
	MOV	r11, #0
	MOV	r12, #0

	LDR	r0, prog_entry
	MOV	pc, r0   ; RESET INTERRUPT

;; ===========================================================================================
prog_entry			.word	_c_int00

;OMAP1610_CONF_STATUS_ADDR       .word   0xFFFE1130
;
; EMIFF init constants
;
EMIFF_SDRAM_CONFIG_ADDR         .word   0xFFFECC20
EMIFF_SDRAM_MRS_ADDR            .word   0xFFFECC24
EMIFF_SDRAM_MRS_NEW_ADDR        .word   0xFFFECC70
EMIFF_SDRAM_EMRS1_ADDR          .word   0xFFFECC78
EMIFF_SDRAM_OPERATION_ADDR      .word   0xFFFECC80
EMIFF_SDRAM_MANUAL_CMD_ADDR     .word   0xFFFECC84
EMIFF_DLL_URD_CONTROL_ADDR      .word   0xFFFECCC0
EMIFF_DLL_LRD_CONTROL_ADDR      .word   0xFFFECCCC
EMIFF_DLL_WRT_CONTROL_ADDR      .word   0xFFFECC64
;
; EMIFF SDRAM Configuration Register
;   -> self refresh disabled
;   -> auto refresh enabled
;   -> SDRAM type 128 Mb, 16 bits bus 4 banks
;   -> SDRAM frequency range : reset value
;   -> power down disabled
;   -> SDRAM clock enabled
;
;mode1_emiff_cfg_val             .word   0x001200B4
emiff_cfg_val              		.word   0x0D039174

; burst full-page length/cas latency = 3
ValueEmifFastMRS                .word   0x00000027

;
; EMIFS init constants
;
EMIFS_CS_CFG1_ADDR              .word   0xFFFECC14
EMIFS_CS_ACFG1_ADDR             .word   0xFFFECC54