usb_otg_ctrl.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//===============================================================================
//            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION          
//
//   Property of Texas Instruments 
//   For  Unrestricted  Internal  Use  Only
//   Unauthorized reproduction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law 
//   as an unpublished work. 
//   Created 2000, (C) Copyright 2000 Texas Instruments.  All rights reserved.
//
//   Filename             : usb_otg.c
//   Date of Module Modification:6/13/02
//   Date of Generation :7/1/02
//   Date of modification : 20/02/2004 Bruno Decroos
//
//===============================================================================
#include "global_types.h"
#include "usb_otg_ctrl.h"
#include "testaccess.h"
#include "errorcodes.h"
#include "result.h"


//---------------------------------------------------------------------
// NAME        : USB_OTG_CTRL_TestResetValue
//
// DESCRIPTION : Test the reset values of USB_OTG_CTRL registers
//
// PARAMETERS  : None
//
// RETURN VALUE: 0 if test OK, else 1
//
// LIMITATIONS : None
//---------------------------------------------------------------------
BOOL USB_OtgCtrlTestResetValue(void)
{
  BOOL Status = 1;

  BEGIN_RESET_MODULE();

    BEGIN_RESET_TEST(USB_OTG_CTRL_OTG_REV_32,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_REV_32,RESERVED,32);
    //USB_OTG_CTRL_OTG_REV,OTG_REV_NB of USB_OTG_CTRL_OTG_REV has unknown reset value;
    END_RESET_TEST();

    BEGIN_RESET_TEST(USB_OTG_CTRL_OTG_SYSCON_1_32,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_1_32,RESERVED1,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_1_32,USB2_TRX_MODE,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_1_32,RESERVED2,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_1_32,USB1_TRX_MODE,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_1_32,RESERVED3,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_1_32,USB0_TRX_MODE,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_1_32,OTG_IDLE_EN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_1_32,HST_IDLE_EN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_1_32,DEV_IDLE_EN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_1_32,RESERVED4,32);
    //USB_OTG_CTRL_OTG_SYSCON_1,RESET_DONE of USB_OTG_CTRL_OTG_SYSCON_1 has unknown reset value;
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_1_32,SOFT_RESET,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_1_32,RESERVED5,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(USB_OTG_CTRL_OTG_SYSCON_2_32,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_2_32,OTG_EN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_2_32,USBx_SYNCHRO,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_2_32,OTG_MST16,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_2_32,SRP_GPDATA,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_2_32,SRP_GPDVBUS,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_2_32,SRP_GPUVBUS,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_2_32,RESERVED2,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_2_32,A_WAIT_VRISE,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_2_32,RESERVED3,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_2_32,B_ASE0_BRST,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_2_32,RESERVED1,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_2_32,SRP_DPW,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_2_32,SRP_DATA,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_2_32,SRP_VBUS,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_2_32,RESERVED4,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_2_32,OTG_PADEN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_2_32,HMC_PADEN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_2_32,UHOST_EN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_2_32,HMC_TLLSPEED,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_2_32,HMC_TLLATTACH,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_SYSCON_2_32,HMC_MODE,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(USB_OTG_CTRL_OTG_CTRL_32,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_CTRL_32,RESERVED1,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_CTRL_32,ASESSVLD,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_CTRL_32,BSESSEND,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_CTRL_32,BSESSVLD,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_CTRL_32,VBUSVLD,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_CTRL_32,ID,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_CTRL_32,DRIVER_SEL,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_CTRL_32,RESERVED2,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_CTRL_32,A_SETB_HNPEN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_CTRL_32,A_BUSREQ,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_CTRL_32,RESERVED3,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_CTRL_32,B_HNPEN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_CTRL_32,B_BUSREQ,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_CTRL_32,OTG_BUSDROP,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_CTRL_32,RESERVED4,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_CTRL_32,OTG_PD,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_CTRL_32,OTG_PU,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_CTRL_32,OTG_DRV_VBUS,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_CTRL_32,OTG_PD_VBUS,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_CTRL_32,OTG_PU_VBUS,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_CTRL_32,OTG_PU_ID,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(USB_OTG_CTRL_OTG_IRQ_EN_32,32);
    //TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_EN_32,RESERVED1,32); suppresed
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_EN_32,DRIVER_SWITCH_EN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_EN_32,RESERVED2,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_EN_32,A_VBUS_ERR_EN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_EN_32,A_REQ_TMROUT_EN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_EN_32,A_SRP_DETECT_EN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_EN_32,B_HNP_FAIL_EN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_EN_32,B_SRP_TMROUT_EN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_EN_32,B_SRP_DONE_EN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_EN_32,B_SRP_STARTED_EN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_EN_32,RESERVED4,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_EN_32,OPRT_CHG_EN,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(USB_OTG_CTRL_OTG_IRQ_SRC_32,32);
    //TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_SRC_32,RESERVED1,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_SRC_32,DRIVER_SWITCH,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_SRC_32,RESERVED2,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_SRC_32,A_VBUS_ERR,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_SRC_32,A_REQ_TMROUT,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_SRC_32,A_SRP_DETECT,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_SRC_32,B_HNP_FAIL,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_SRC_32,B_SRP_TMROUT,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_SRC_32,B_SRP_DONE,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_SRC_32,B_SRP_STARTED,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_SRC_32,RESERVED4,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_IRQ_SRC_32,OPRT_CHG,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(USB_OTG_CTRL_OTG_OUTCTRL_32,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_OUTCTRL_32,RESERVED1,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_OUTCTRL_32,OTGVPD,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_OUTCTRL_32,OTGVPU,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_OUTCTRL_32,OTGPUID,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_OUTCTRL_32,RESERVED2,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_OUTCTRL_32,USB2VDR,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_OUTCTRL_32,USB2PDEN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_OUTCTRL_32,USB2PUEN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_OUTCTRL_32,RESERVED3,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_OUTCTRL_32,USB1VDR,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_OUTCTRL_32,USB1PDEN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_OUTCTRL_32,USB1PUEN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_OUTCTRL_32,RESERVED4,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_OUTCTRL_32,USB0VDR,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_OUTCTRL_32,USB0PDEN,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_OUTCTRL_32,USB0PUEN,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(USB_OTG_CTRL_OTG_TEST_32,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_TEST_32,TEST_UNLOCK,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_TEST_32,RESERVED2,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_TEST_32,IRQ_OTG,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_TEST_32,OTG_FSM_STATE,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(USB_OTG_CTRL_OTG_VC_32,32);
    TEST_FIELD_RESET(USB_OTG_CTRL_OTG_VC_32,VC,32);
    //USB_OTG_CTRL_OTG_VC,VC of USB_OTG_CTRL_OTG_VC has unknown reset value;
    END_RESET_TEST();

    if ( GlobalStatus == TEST_OK )
      Status = 0;
    else
      Status = 1;

  END_RESET_MODULE();

  return Status;
}

//---------------------------------------------------------------------
// NAME        : USB_OtgCtrlTestRegistersAccess
//
// DESCRIPTION : Test the access to USB_OTG_CTRL registers
//
// PARAMETERS  : None
//
// RETURN VALUE: 0 if test OK, else 1
//
// LIMITATIONS : None
//---------------------------------------------------------------------
BOOL USB_OtgCtrlTestRegistersAccess(void)
{
  BOOL Status = 1;

  BEGIN_ACCESS_MODULE();

    BEGIN_RW_TEST(USB_OTG_CTRL_OTG_SYSCON_1_32,32);
    //USB_OTG_CTRL_OTG_SYSCON_1_32,RESERVED1 must be written by software with 0's
    RW_PREPARE_WRITE(USB_OTG_CTRL_OTG_SYSCON_1_32,USB2_TRX_MODE,32);
    //USB_OTG_CTRL_OTG_SYSCON_1_32,RESERVED2 must be written by software with 0's
    RW_PREPARE_WRITE(USB_OTG_CTRL_OTG_SYSCON_1_32,USB1_TRX_MODE,32);
    //USB_OTG_CTRL_OTG_SYSCON_1_32,RESERVED3 must be written by software with 0's
    RW_PREPARE_WRITE(USB_OTG_CTRL_OTG_SYSCON_1_32,USB0_TRX_MODE,32);
    RW_PREPARE_WRITE(USB_OTG_CTRL_OTG_SYSCON_1_32,OTG_IDLE_EN,32);
    RW_PREPARE_WRITE(USB_OTG_CTRL_OTG_SYSCON_1_32,HST_IDLE_EN,32);
    RW_PREPARE_WRITE(USB_OTG_CTRL_OTG_SYSCON_1_32,DEV_IDLE_EN,32);
    //USB_OTG_CTRL_OTG_SYSCON_1_32,RESERVED4 must be written by software with 0's
    //USB_OTG_CTRL_OTG_SYSCON_1_32,RESET_DONE is Read Only
    RW_PREPARE_WRITE(USB_OTG_CTRL_OTG_SYSCON_1_32,SOFT_RESET,32);
    //USB_OTG_CTRL_OTG_SYSCON_1_32,RESERVED5 must be written by software with 0's
    RW_WRITE(USB_OTG_CTRL_OTG_SYSCON_1_32);
    //USB_OTG_CTRL_OTG_SYSCON_1_32,RESERVED1 when read, any RESERVED bit returns 0
    RW_TEST_READ(USB_OTG_CTRL_OTG_SYSCON_1_32,USB2_TRX_MODE,32);
    //USB_OTG_CTRL_OTG_SYSCON_1_32,RESERVED2 when read, any RESERVED bit returns 0
    RW_TEST_READ(USB_OTG_CTRL_OTG_SYSCON_1_32,USB1_TRX_MODE,32);
    //USB_OTG_CTRL_OTG_SYSCON_1_32,RESERVED3 when read, any RESERVED bit returns 0
    RW_TEST_READ(USB_OTG_CTRL_OTG_SYSCON_1_32,USB0_TRX_MODE,32);
    RW_TEST_READ(USB_OTG_CTRL_OTG_SYSCON_1_32,OTG_IDLE_EN,32);
    RW_TEST_READ(USB_OTG_CTRL_OTG_SYSCON_1_32,HST_IDLE_EN,32);
    RW_TEST_READ(USB_OTG_CTRL_OTG_SYSCON_1_32,DEV_IDLE_EN,32);
    //USB_OTG_CTRL_OTG_SYSCON_1_32,RESERVED4 when read, any RESERVED bit returns 0
    //USB_OTG_CTRL_OTG_SYSCON_1_32,RESET_DONE is Read Only
    //USB_OTG_CTRL_OTG_SYSCON_1_32,SOFT_RESET during reads, this bit ALWAYS return 0
    //RW_TEST_READ(USB_OTG_CTRL_OTG_SYSCON_1_32,SOFT_RESET,32);
    //USB_OTG_CTRL_OTG_SYSCON_1_32,RESERVED5 when read, any RESERVED bit returns 0
    RW_WRITE_PREVIOUS_VALUE(USB_OTG_CTRL_OTG_SYSCON_1_32);
    END_RW_TEST();

    BEGIN_RW_TEST(USB_OTG_CTRL_OTG_SYSCON_2_32,32);
    RW_PREPARE_WRITE(USB_OTG_CTRL_OTG_SYSCON_2_32,OTG_EN,32);
    RW_PREPARE_WRITE(USB_OTG_CTRL_OTG_SYSCON_2_32,USBx_SYNCHRO,32);
    RW_PREPARE_WRITE(USB_OTG_CTRL_OTG_SYSCON_2_32,OTG_MST16,32);
    RW_PREPARE_WRITE(USB_OTG_CTRL_OTG_SYSCON_2_32,SRP_GPDATA,32);