testbench.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//===============================================================================
//            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
//   Property of Texas Instruments
//   For  Unrestricted  Internal  Use  Only
//   Unauthorized reproduction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work.
//   Created 2000, (C) Copyright 2000 Texas Instruments.  All rights reserved.
//===============================================================================
//
#include "gpio.h"
#include "mapping.h"
#include "testbench.h"
#include "configuration.h"
#include "omap_32_emiff.h"

//-------------------------------------------------------------------------------
// NAME         : TSTB_SetTbSync
//
// DESCRIPTION  : - Init the GPIO direction for synchro signals
//                 GMC_RDY = input / GMC_ERROR = input / GMC_SYNC = OUTPUT
//                - drive GMC_SYNC pin to '0'
// PARAMETERS   : none
//
// RETURN VALUE : None
//
//--------------------------------------------------------------------------------
void TSTB_SetTbSync(void)
{
  // sets direction
  GPIO_SetOeBit(GPIO1_BASE_ADDR_ARM, GMC_ERR);
  GPIO_SetOeBit(GPIO1_BASE_ADDR_ARM, GMC_RDY);
  GPIO_ClearOeBit(GPIO1_BASE_ADDR_ARM, GMC_SYNC);
  // sets sync to 0
  GPIO_ClearDataOutBit(GPIO1_BASE_ADDR_ARM, GMC_SYNC);
}


//-------------------------------------------------------------------------------
// NAME         : TSTB_DoSync
//
// DESCRIPTION  : - Generate a GMC_SYNC pulse to the testbench when GMC_RDY is '1'
//
// PARAMETERS   : none
//
// RETURN VALUE : None
//
//------------------------------------------------------------------------------
void TSTB_DoSync(void)
{
   while (GPIO_GetInputPin(GPIO1_BASE_ADDR_ARM, GMC_RDY) != 1);
     GPIO_SetDataOutBit(GPIO1_BASE_ADDR_ARM, GMC_SYNC);
   while (GPIO_GetInputPin(GPIO1_BASE_ADDR_ARM, GMC_RDY) != 0);
     GPIO_ClearDataOutBit(GPIO1_BASE_ADDR_ARM, GMC_SYNC);
}



BOOL TSTB_TbhCcpLineCheck (UWORD32 *const inBuffer,
                        int            inLineCount,
                        int            inStep)
/*
 *
 */
{
  register int lvLine;
  register int lvByte;

  for (lvLine = 0;
       lvLine < inLineCount;
       lvLine++)
  for (lvByte = 0;
       lvByte < TBH_CCP_LINE_LENGTH;
       lvByte += (4*inStep))
  {
    /*
     * This mumbo-jumbo is necessary because of the byte ordering
     * of the received data; i.e. 4,3,2,1,8,7,6,5,12,11,10....
    if (inBuffer[lv_i] !=
         ((((lv_i % TBH_CCP_LINE_LENGTH) / sizeof(UWORD32)) * sizeof(UWORD32)) +
                    (sizeof(UWORD32) - (lv_i % sizeof(UWORD32)))))
     */


    if (inBuffer[((lvLine * TBH_CCP_LINE_LENGTH) + lvByte) / sizeof (UWORD32)] !=
                      (((lvByte + 1) << 24) | ((lvByte + 2) << 16) |
                       ((lvByte + 3) <<  8) | ((lvByte + 4) <<  0)))
      return (FALSE);
  }

  return (TRUE);
}


//-------------------------------------------------------------------------------
// NAME         : TSTB_ConfigureEmiff
//
// DESCRIPTION  : This function allows to configure EMIFF in SDR, DDR, or
//                Mobile DDR
// PARAMETERS   : SDRAM type
//
// RETURN VALUE : None
//
//------------------------------------------------------------------------------

void TSTB_ConfigureEmiff(UWORD32 sdram_type)
{


  switch (sdram_type)
    {
    case SDR_SDRAM:
      {
        //SDR SDRAM configuration
        //  -> SDRAM SDR  bits [1:0]
	//  -> HPHB mode  bits [3:2]
        EMIFF_SDRAM_OPERATION_REG  = 0x00000004;

	//EMIFF SDRAM Configuration Register
	//   -> self refresh disabled
	//   -> auto refresh enabled
	//   -> SDRAM type 256 Mb, 16 bits bus 4 banks
	//   -> SDRAM frequency range : reset value
	//   -> power down disabled
	//   -> SDRAM clock enabled
	//EMIFF_EMIFF_SDRAM_CONFIG = 0x002400F4;
        EMIFF_EMIFF_SDRAM_CONFIG = 0x0F0391F6; //0x0D039174;
        EMIFF_EMIFF_MRS = 0x00000037;

       break;
      }

    case DDR_SDRAM:
      {
        //DDR SDRAM K4X28163 configuration
        //8Mx16 bits
        //mapping 0x10000000-0x10FFFFFF
        //LATENCY ...

        //EMIFF Priority Register default 0x000000000

        //EMIFF SDRAM Configuration Register
        //[31:30] = must be 00
        //reserved
        //[29:28] = 00
        //memory size=>64 Mb
        //[27:24] = 0000
        //SDRAM clk enabled/PWD disabled/latency SDF0
        //[23:8]  = 0x6188
        //default value for autorefresh counter
        //[7:4] = 0111
	//data bus size=>16 # banks=>4
	//[3:0]   = 0000
	//autorefresh disabled/reserved/self refresh disabled
	//value in intvecs => EMIFF_EMIFF_SDRAM_CONFIG = 0x0D039174;
	EMIFF_EMIFF_SDRAM_CONFIG = 0x00618870;
	//EMIFF SDRAM Operation Register
	//[31:4] = 0x0000000
	//bank1-4 timeout value = 4
	//[3:0]  = 1001
	//PM0 mode/regular DDR SDRAM
	EMIFF_SDRAM_OPERATION_REG  = 0x08102049;
	break;
      }

    case DDR_MOBILE:
      {
        //DDR SDRAM K4X28163 configuration
        //  -> mobile DDR
	//  -> HPHB mode
        EMIFF_SDRAM_OPERATION_REG  = 0x00000007;

	//EMIFF SDRAM Configuration Register
	//   -> self refresh disabled
	//   -> auto refresh enabled
	//   -> SDRAM type 128 Mb, 16 bits bus 4 banks
	//   -> SDRAM frequency range : reset value
	//   -> power down disabled
	//   -> SDRAM clock enabled
	EMIFF_EMIFF_SDRAM_CONFIG = 0x001200B4;

	break;
      }
    default:
      break;
    }
    //SDRAM POWER-UP SEQUENCE

}




/* EOF */