📄 uarttest.c
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//------------------------------------------------
// Configure DMA channel 0 for tx to uart
//------------------------------------------------
DMAT_ConfigureRheaMemTransfert(DMA_CHANNEL_0,
DMA_SDRAM, (UWORD32) ptr_tx_buffer,
DMA_RHEA, (UWORD32) UART_IRDA_ADDR,
DMA_TYPE_8_BITS, // perif rhea size
nb_byte_to_transmit,
UART_IRDA_TX_GDMA_REQ);
//-----------------------------------------------------------------
// Configure DMA channel 1 for rx from uart
// WARNING : crc coded on 2 bytes is received
// so add 2 bytes in reception
//-----------------------------------------------------------------
DMAT_ConfigureRheaMemTransfert(DMA_CHANNEL_1,
DMA_RHEA, (UWORD32) UART_IRDA_ADDR,
DMA_SDRAM, (UWORD32) ptr_rx_buffer,
DMA_TYPE_8_BITS, // perif rhea size
nb_byte_to_transmit + 2,
UART_IRDA_RX_GDMA_REQ);
//----------------------------------------------------
// ENABLE CHANNELS 0 & 1
//----------------------------------------------------
*end_dma_channel_0=False;
*end_dma_channel_1=False;
DMA_EnableChannel(DMA_CHANNEL_0); // enable transmit dma channel
DMA_EnableChannel(DMA_CHANNEL_1); // enable receive dma channel
// write again in SCR register for generating a new Dma_nrequest
UIRD_InitScr(UARTIRDA_SCR_SET_DMA_MODE ,
UARTIRDA_nDMA_REQ_0_in_TX_1_in_RX,
UARTIRDA_THR_IT_NORMAL_MODE,
UARTIRDA_NO_WAKEUP,
UARTIRDA_MASK_DSR_IT,
UARTIRDA_TxTriggranu1,
UARTIRDA_RxTriggranu1);
//---------------------------------------------------
// WAIT FOR IT DMA of end of Transmission
//---------------------------------------------------
// Put arm in idle (wait for interrupt) if interrupt isn't yet incoming
if (*end_dma_channel_0 == False)
CLKRST_SetIdle(IDLE_INT_WKUP);
//---------------------------------------------------
// WAIT FOR IT DMA of end of Transmission -
//---------------------------------------------------
while (*end_dma_channel_0 ==False) ;
//----------------------------------------------------------
// Wait for IT DMA of Reception -
//----------------------------------------------------------
if (*end_dma_channel_1 == False)
CLKRST_SetIdle(IDLE_INT_WKUP);
while (*end_dma_channel_1 ==False) ;
//--------------------------------------------------------------------
// Check the data read match the written data
// and that the overflow area is not overwritten
//--------------------------------------------------------------------
ok=True;
for (i=0; i <nb_byte_to_transmit; i++)
{
if (ptr_tx_buffer[i] != ptr_rx_buffer[i])
ok=False;
}
return(ok);
}
/*
//--------------------------------------------------------------------
// NAME : UTST_ModemWithDma
// DESCRIPTION: performs uart test in DMA mode (uart is in internal loopback)
// Transfers are done from and to EMIF slow (CS0)
// Disable DMA Channel 0 & 1
// Configure UART in Loop Back TX --> RX
// Write overflow data Into destination area
// Fill DATA to be transfered
// Enable channel 0 & 1
// Wait for IT DMA of Sending
// Disable Transmitter Channel #0
// Wait for IT DMA of Reception
// Check the data read match the written data
// and that the overflow area is not overwritten
//
// PARAMETERS :
// emif_src_address,
// emif_dst_address
// nb_byte_to_transmit
// end_dma_channel_0
// end_dma_channel_1
// RESTRICTION : source and destination address should correspond to EMIF slow Interface
// nb_byte_to_transmit should be a multiple of 4
// RETURN VALUE: RES_OK on success otherwise RES_BAD
//---------------------------------------------------------------------
UWORD16 UTST_ModemWithDma(UWORD32 emif_src_address,
UWORD32 emif_dst_address,
UWORD8 nb_byte_to_transmit,
volatile BOOL * const end_dma_channel_0,
volatile BOOL * const end_dma_channel_1)
{
UWORD8 * ptr_tx_buffer;
UWORD8 * ptr_rx_buffer; // one byte more for checking overflow
UWORD8 i;
BOOL ok;
ptr_tx_buffer = (UWORD8 *) emif_src_address ;
ptr_rx_buffer = (UWORD8 *) emif_dst_address ;
asic_configure_dma_for_uart_modem();
UTST_InitUartModem ();
UMOD_ReadLsr();
UMOD_ReadIir();
//----------------------------------------------------
// 1) DISABLE CHANNELS 0 & 1
//----------------------------------------------------
DMA_DisableChannel(DMA_CHANNEL_0); // disable transmit dma channel
DMA_DisableChannel(DMA_CHANNEL_1); // disable rx dma channel
//----------------------------------------------------
// 2) CONFIGURE UART
//----------------------------------------------------
//DMA MODE FIFO CONTROL REGISTER (FCR) not used , Supplement Control Register set DMA MODE
//DMA Mode 2 ARM_nDMA_REQ[0] in TX UART MODEM
UMOD_InitScr(UARTMOD_FCR_SET_DMA_MODE ,
UARTMOD_nDMA_REQ_0_in_TX_1_in_RX,
UARTMOD_THR_IT_NORMAL_MODE,
UARTMOD_NO_WAKEUP, UARTMOD_MASK_DSR_IT);//2 new fields
//trigger Level register (4)
UMOD_InitTlr(UARTMOD_TX_FIFO_TRIG_DMA_4_TO_FILLUP,
UARTMOD_RX_FIFO_TRIG_DMA_4_TO_GET);
UMOD_ReadIir();
//----------------------------------------------------------
// init. to check transfer overflow
//----------------------------------------------------------
* (ptr_rx_buffer + nb_byte_to_transmit)=0x55;
//--------------------------------------------------------------
// Fill DATA into memory
// to send to UART MODEM Rhea peripheral -
//--------------------------------------------------------------
for (i=0; i <nb_byte_to_transmit; i++)
{
* (ptr_tx_buffer+i) = i+INITIAL_VALUE;
}
//------------------------------------------------
// Configure DMA channel 0 for tx to modem
//------------------------------------------------
DMA_ConfigureEmifToRhea(DMA_CHANNEL_0, // channel id
DMA_LOW_PRIORITY, // priority
(UWORD32) ptr_tx_buffer, // source
RHEA_STROBE0_CHIP_SELECT_0, // UART ship select
(UWORD16)UART_MODEM_ADDR, // destination adresse (constante)
nb_byte_to_transmit, // transfert length
RHEA_BITS8_SIZE, // acces size
DMA_AUTOINIT_DISABLE, // no auto init mode
DMA_DISABLE_HALF_BLOCK_TRANSFER_IT);// no interrupt at half block transfert
//-----------------------------------------------------------------
// Configure DMA channel 1 for rx from modem
//-----------------------------------------------------------------
DMA_ConfigureRheaToEmif(DMA_CHANNEL_1, // channel id
DMA_LOW_PRIORITY, // priority
(UWORD16)UART_MODEM_ADDR, // constante source
RHEA_STROBE0_CHIP_SELECT_0, // UART ship select
(UWORD32) ptr_rx_buffer, // destination adresse (auto increment)
nb_byte_to_transmit, // transfert length
RHEA_BITS8_SIZE, // acces size
DMA_AUTOINIT_DISABLE, // no auto init mode
DMA_DISABLE_HALF_BLOCK_TRANSFER_IT);// no interrupt at half block transfert
//----------------------------------------------------
// ENABLE CHANNELS 0 & 1
//----------------------------------------------------
*end_dma_channel_0=False;
*end_dma_channel_1=False;
DMA_EnableChannel(DMA_CHANNEL_0); // enable transmit dma channel
DMA_EnableChannel(DMA_CHANNEL_1); // enable receive dma channel
// write again in SCR register for generating a new Dma_nrequest
UMOD_InitScr(UARTMOD_SCR_SET_DMA_MODE ,
UARTMOD_nDMA_REQ_0_in_TX_1_in_RX,
UARTMOD_THR_IT_NORMAL_MODE,
UARTMOD_NO_WAKEUP, UARTMOD_MASK_DSR_IT);//2 new fields
CLKA_ConfigIdleModule( (BOOL)SET_IN_IDLE, //TimState
(BOOL)SET_NOT_IDLE, //DpllState
(BOOL)SET_NOT_IDLE, //IntMemState (dma, mem ...)
(BOOL)SET_IN_IDLE, //LcdState
(BOOL)SET_NOT_IDLE, //PerState
(BOOL)SET_NOT_IDLE, //XorpState
(BOOL)SET_IN_IDLE); //WdtState
// Put arm in idle (wait for interrupt) if interrput isn't yet incoming
if (*end_dma_channel_0 == False)
CLKA_SetIdle((BOOL)IDLE_WAITFOR_INT_WKUP);
//---------------------------------------------------
// WAIT FOR IT DMA of end of Transmission -
//---------------------------------------------------
while (*end_dma_channel_0 ==False) ;
//----------------------------------------------------------
// Disable DMA channel 0
//----------------------------------------------------------
DMA_DisableChannel(DMA_CHANNEL_0); // disable transmit dma channel
//----------------------------------------------------------
// Wait for IT DMA of Reception -
//----------------------------------------------------------
while (*end_dma_channel_1 ==False) ;
//--------------------------------------------------------------------
// Check the data read match the written data
// and that the overflow area is not overwritten -
//--------------------------------------------------------------------
ok=True;
for (i=0; i <nb_byte_to_transmit; i++)
{
if (*(ptr_tx_buffer+i) != *(ptr_rx_buffer+i))
ok=False;
}
// check dma overflow
if (*(ptr_rx_buffer+nb_byte_to_transmit)!=0x55)
ok=False;
if (ok)
return(RES_OK);
else
return(RES_BAD);
}
//--------------------------------------------------------------------
// NAME : UARTTEST_irda_sir_mode_with_dma
// DESCRIPTION:
//
// Disable DMA Channel 0 & 1
// Configure UART (with external Loop Back TX --> RX)
// Write overflow data Into destination area
// Fill DATA to be transfered
// Enable channel 0 & 1
// Wait for IT DMA of Sending
// Disable Transmitter Channel #0
// Wait for IT DMA of Reception
// Check the data read match the written data
// and that the overflow area is not overwritten
//
// PARAMETERS : Counters of irda & dma IRQs
// RETURN VALUE: RES_OK on success otherwise RES_BAD
//---------------------------------------------------------------------
#define DMA_TRANSFERT_LENGTH 68
UWORD8 tx_buffer[DMA_TRANSFERT_LENGTH ];
UWORD8 rx_buffer[DMA_TRANSFERT_LENGTH+1]; // one byte more for checking overflow
UWORD16 UARTTEST_irda_sir_mode_with_dma(volatile BOOL * const end_dma_channel_0,
volatile BOOL * const end_dma_channel_1,
UWORD8 * const irda_irq_count,
UWORD16 transfert_length)
{
UWORD32 i;
BOOL ok;
//---------------------------------------------------
// 0) Initialize UART/IRDA
//---------------------------------------------------
UART_TestInitUartIrdaSirMode(transfert_length,
UARTTEST_EXTERNAL_LOOPBACK,
irda_irq_count);
UMOD_ReadLsr();
UMOD_ReadIir();
//----------------------------------------------------
// 1) DISABLE CHANNELS 0 & 1
//----------------------------------------------------
DMA_DisableChannel(DMA_CHANNEL_0); // disable transmit dma channel
DMA_DisableChannel(DMA_CHANNEL_1); // disable rx dma channel
//----------------------------------------------------
// 2) CONFIGURE UART
//----------------------------------------------------
//DMA MODE FIFO CONTROL REGISTER (FCR) not used , Supplement Control Register set DMA MODE
//DMA Mode 1 ARM_nDMA_REQ[0] in TX UART IRDA
UIRD_InitScr(UARTIRDA_SCR_SET_DMA_MODE,
UARTIRDA_nDMA_REQ_0_in_TX_1_in_RX,
UARTIRDA_THR_IT_NORMAL_MODE,
UARTIRDA_NO_WAKEUP, UARTIRDA_MASK_DSR_IT);
//trigger Level register (4)
UMOD_InitTlr(UARTMOD_TX_FIFO_TRIG_DMA_4_TO_FILLUP,
UARTMOD_RX_FIFO_TRIG_DMA_4_TO_GET);
UMOD_ReadIir();
//----------------------------------------------------------
// init. to check transfer overflow
//----------------------------------------------------------
rx_buffer[transfert_length]=0x55;
//--------------------------------------------------------------
// Fill DATA into memory to send to UART IRDA
//--------------------------------------------------------------
for (i=0; i <transfert_length; i++)
{
tx_buffer[i] = i + INITIAL_VALUE;
}
//------------------------------------------------
// Configure DMA channel 0 for tx to irda
//------------------------------------------------
DMA_ConfigureImifToRhea(DMA_CHANNEL_0, // channel id
DMA_LOW_PRIORITY, // priority
(UWORD32)&tx_buffer, // source
RHEA_STROBE0_CHIP_SELECT_1, // UART IRDA ship select
(UWORD16)UART_IRDA_ADDR, // destination adress (constant)
transfert_length, // transfert length
RHEA_BITS8_SIZE, // acces size
DMA_AUTOINIT_DISABLE, // no auto init mode
DMA_DISABLE_HALF_BLOCK_TRANSFER_IT);// no interrupt at half block transfert
//-------------------------------------------------
// Configure DMA channel 1 for rx from irda
//-------------------------------------------------
DMA_ConfigureRheaToImif(DMA_CHANNEL_1, // channel id
DMA_LOW_PRIORITY, // priority
(UWORD16)UART_IRDA_ADDR, // constante source
RHEA_STROBE0_CHIP_SELECT_1, // UART IRDA ship select
(UWORD32)&rx_buffer, // destination adress (auto increment)
transfert_length, // transfert length
RHEA_BITS8_SIZE, // acces size
DMA_AUTOINIT_DISABLE, // no auto init mode
DMA_DISABLE_HALF_BLOCK_TRANSFER_IT);// no interrupt at half block transfert
//-------------------------------------------------
// ENABLE CHANNELS 0 & 1
//-------------------------------------------------
// *end_dma_channel_0=False;
// *end_dma_channel_1=False;
DMA_EnableChannel(DMA_CHANNEL_0); // enable transmit dma channel
DMA_EnableChannel(DMA_CHANNEL_1); // enable receive dma channel
*end_dma_channel_0=False;
*end_dma_channel_1=False;
// write again in SCR register for generating a new Dma_nrequest
UIRD_InitScr(UARTIRDA_SCR_SET_DMA_MODE ,
UARTIRDA_nDMA_REQ_0_in_TX_1_in_RX,
UARTIRDA_THR_IT_NORMAL_MODE,
UARTIRDA_NO_WAKEUP, UARTIRDA_MASK_DSR_IT);
//---------------------------------------------------
// WAIT FOR IT DMA of end of Transmission
//---------------------------------------------------
i = 0;
while ((*end_dma_channel_0 ==False) && (i < 2000)) { i++; }
if (i == 2000)
{
RES_Set(0xDEAD);
RES_StopVhdl();
}
//---------------------------------------------------
// Disable DMA channel 0
//---------------------------------------------------
DMA_DisableChannel(DMA_CHANNEL_0); //disable transmit dma channel
//---------------------------------------------------
// Wait for IT DMA of Reception
//---------------------------------------------------
i = 0;
while ((*end_dma_channel_1 ==False) && (i < 2000)) { i++; }
if (i == 2000)
{
RES_Set(0xDEAD);
RES_StopVhdl();
}
//--------------------------------------------------------------------
// Check the data read match the written data
// and that the overflow area is not overwritten
//--------------------------------------------------------------------
ok=True;
for (i=0; i <transfert_length; i++)
{
if (tx_buffer[i] != rx_buffer[i])
ok=False;
}
// check dma overflow
if (rx_buffer[transfert_length]!=0x55)
ok=False;
if (ok)
return(RES_OK);
else
return(RES_BAD);
}
*/
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