uarttest.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

                   UARTIRDA_ENABLE_WRITE_IER,
                   UARTIRDA_DISABLE_SPECIAL_CHAR_DETECT,
                   UARTIRDA_DISABLE_AUTO_RTS,
                   UARTIRDA_DISABLE_AUTO_CTS);	
  
  //Set no Interrupt config & Disable sleep mode for config divisor latches
  UIRD_IerMaskAllIt();
  

 // enable divisor 6.5 if uart frequency is 12 MHz
 if (Enable6_5divider)
     UARTIRDA_OSC_REG=1;
     
//  set divider latch value
 UIRD_InitDivLatch((DividerLatch&0xFF),((DividerLatch>>8)&0xFF));
 
 if ((val=UIRD_ReadDll()) != (DividerLatch&0xFF) )
   {
      RES_Set(val);
     ok &= False;
   }
 
 
 if ((val=UIRD_ReadDlh()) != ((DividerLatch>>8)&0xFF) )
   {
      RES_Set(val);
     ok &= False;
   }


  
  //set disable sleep mode
  UIRD_IerMaskAllIt();
  
  
  //---  End sequence for change baud rate ---
  
  
  // clear FIFO
  UIRD_InitFcr(UARTIRDA_DISABLE_FIFOS,  
                   UARTIRDA_CLEAR_RX_FIFO, 
                   UARTIRDA_CLEAR_TX_FIFO,  
                   UARTIRDA_DMA_MODE_0, 
                   UARTIRDA_TX_8_SPACES_FIFO_TRIGGER,
                   UARTIRDA_RX_8_CHARS_FIFO_TRIGGER);

  //--- Program FIFO and DMA mode  ---
  
  //FIFO BYPASS in TX and Rx =0, clear FIFO Rx =0 don't care, Clear FIFO tx= 0 don't care,
  //DMA mode 0 =1 single character transfers,  trig. TX FIFO don't care , trig.RX FIFO don't care
  UIRD_InitFcr(UARTIRDA_ENABLE_FIFOS,
		   UARTIRDA_NOCHANGE_RX_FIFO,
		   UARTIRDA_NOCHANGE_TX_FIFO,
		   UARTIRDA_DMA_MODE_0,
		   UARTIRDA_TX_8_SPACES_FIFO_TRIGGER,
		   UARTIRDA_RX_8_CHARS_FIFO_TRIGGER);                     
  
  if (external_loopback)
    // external loopback
    UIRD_InitMcr(UARTIRDA_FAX_MODE_ENABLE,
		     UARTIRDA_OUTPUT_REQUEST_TO_SEND_ENABLE,
		     UARTIRDA_NO_LOOPBACK,
		     UARTIRDA_DISABLE_XON_ANY_FCT,
		     UARTIRDA_ENABLE_TCR_TLR_ACCESS,
		     UARTIRDA_DIV_CLOCK_INPUT_NO_ACTION);  // Force DCD and RTS low
  
  else
    // internal loopback
    UIRD_InitMcr(UARTIRDA_FAX_MODE_ENABLE,
		     UARTIRDA_OUTPUT_REQUEST_TO_SEND_ENABLE,
		     UARTIRDA_LOOPBACK,
		     UARTIRDA_DISABLE_XON_ANY_FCT,
		     UARTIRDA_ENABLE_TCR_TLR_ACCESS,
		     UARTIRDA_DIV_CLOCK_INPUT_NO_ACTION);  // Force DCD and RTS low
    
  
  UIRD_ReadIir();
  *irda_irq_count = 0;
  
  
  //init UART MODE
  
  // very important !! set this register after set clock, DLL,DLH,LCR ...
  UIRD_InitMdr1(UARTIRDA_UART_SELECT, 
                        UARTIRDA_DISABLE_SLEEP, 
                        UARTIRDA_ASAP_START, 
                        UARTIRDA_FRAME_LENGTH_METHOD);
  
  // --- Enable interrupts used
  //  set Interrupt config
  UIRD_InitIer(UARTIRDA_RHR_IT_ENABLE,
                       UARTIRDA_THR_IT_ENABLE,
                       UARTIRDA_LINE_STS_IT_ENABLE,
                       UARTIRDA_MODEM_STS_IT_ENABLE,
                       UARTIRDA_MASK_SLEEP_MODE,
                       UARTIRDA_MASK_XOFF_IT,
                       UARTIRDA_RTS_IT_ENABLE,
                       UARTIRDA_CTS_IT_ENABLE);
  
  // wait INTERRUPT THR empty
  do
    {
      UIRD_ReadIir();
    }
  while ( *irda_irq_count == 0);   
  
  
}

//--------------------------------------------------------------------
// NAME       : UART_TestIrdaSendValue
//---------------------------------------------------------------------
void UART_TestIrdaSendValue(UWORD8 nb_byte_to_transmit)
{
  UWORD32 i;
  //--------------------------------------
  // SEND VALUE                          -
  //--------------------------------------
  for (i=0; i<nb_byte_to_transmit; i++)
    {
      UIRD_Send(i+ INITIAL_VALUE);                    
    }
  
  //----------------------------------------------
  // CHECK STATUS OF SENDER                      -
  //----------------------------------------------
  UIRD_Readlsr();
  
  // wait transmit data is ended, hold and shift register are empty
  while ( UIRD_IsTransmitAndHoldRegNotEmpty() ) { };     
  
}


BOOL UART_TestIrdaInUartModeReceiveAndCheck(UWORD8 nb_byte_to_transmit)
{
  UWORD8 val;
  UWORD32 i;
  BOOL ok = True;

  //----------------------------------------------
  // CHECK STATUS OF RECEIVER                    -
  //----------------------------------------------
  UIRD_Readlsr();  
  
  //--------------------------------------------------
  //  UART CATCH BACK THE CHARACTERS AND CHECK       -
  //--------------------------------------------------
  i=0;
  ok=True;
  while (i < nb_byte_to_transmit)
    {
    // before read verify one character is in FIFO receive
    if ( UIRD_RxFifoIsNotEmptyUartMode() )                
	   {
	   val = UIRD_Read();
	   if (val != (i+ INITIAL_VALUE))
	      {
	      ok = False;
			RES_Set(START_ARRAY_DATA);
			RES_Set(i); // index data
			RES_Set(i+INITIAL_VALUE); // expected data
			RES_Set(val); // read data
			RES_Set(END_ARRAY_DATA);
	      }//endif data
	    i++;
	    }//endif IsnotEmpty
    }//endwhile
  
return (ok) ;
 
}


//--------------------------------------------------------------------
// NAME       : UTST_ModemWithDmaUsingSdram
// DESCRIPTION: performs uart test in DMA mode (uart is in internal loopback)
//              Transfers are done from and to EMIF Fast (CS4: SDRAM)
//  Disable DMA Channel 0 & 1 
//  Configure UART in Loop Back TX --> RX                                 
//  Write overflow data Into destination area 
//  Fill DATA to be transfered
//  Enable channel 0 & 1
//  Wait for IT DMA of Sending  
//  Disable Transmitter Channel #0        
//  Wait for IT DMA of Reception                      
//  Check the data read match the written data        
//   and that the overflow area is not overwritten                  
//                                      
// PARAMETERS  : 
//    sdram_src_address,
//    sdram_dst_address
//    nb_byte_to_transmit
//    end_dma_channel_0 
//    end_dma_channel_1
// RESTRICTION : source and destination address should correspond to EMIF slow Interface
//						nb_byte_to_transmit should be a multiple of 4
// RETURN VALUE: True if success otherwise False
//---------------------------------------------------------------------


BOOL UTST_ModemWithDmaUsingSdram(UARTMOD_UartType_t UartType,
														  BOOL Enable6_5divider,
														  UWORD32 sdram_src_address,
	                                    	  UWORD32 sdram_dst_address,
				            						  UWORD8 nb_byte_to_transmit,
				            						  volatile BOOL * const end_dma_channel_0, 
                                            volatile BOOL * const end_dma_channel_1)
  
{
UWORD8 * ptr_tx_buffer;
UWORD8 * ptr_rx_buffer; // one byte more for checking overflow
UWORD8 i;
BOOL ok;

UWORD8 synchro_tx;
UWORD8 synchro_rx;
UWORD32 uart_address;
  
  ptr_tx_buffer = (UWORD8 *) sdram_src_address ;
  ptr_rx_buffer = (UWORD8 *) sdram_dst_address ;
  
  
  UTST_InitUartModem (UartType,Enable6_5divider); 
  UMOD_ReadLsr(UartType);
  UMOD_ReadIir(UartType);
  

  
  //----------------------------------------------------
  // CONFIGURE UART
  //----------------------------------------------------
  //DMA MODE FIFO CONTROL REGISTER (FCR) not used , Supplement Control Register set DMA MODE
  //DMA Mode 2 ARM_nDMA_REQ[0] in TX UART MODEM 
  UMOD_InitScr(UARTMOD_SCR_SET_DMA_MODE  , 
                  UARTMOD_nDMA_REQ_0_in_TX_1_in_RX, 
                  UARTMOD_THR_IT_NORMAL_MODE, 
                  UARTMOD_NO_WAKEUP, UARTMOD_MASK_DSR_IT,UARTMOD_Txtriggranu0,UARTMOD_Rxtriggranu0,UartType);
  
/* level are set by fcr register
  //trigger Level register (4)
  UMOD_InitTlr(UARTMOD_TX_FIFO_TRIG_DMA_4_TO_FILLUP,
                  UARTMOD_RX_FIFO_TRIG_DMA_4_TO_GET,
						UartType);
*/  
  UMOD_ReadIir(UartType);
  
  //----------------------------------------------------------
  // init. to check transfer overflow 
  //----------------------------------------------------------
  * (ptr_rx_buffer + nb_byte_to_transmit)=0x55;
  
  //--------------------------------------------------------------
  // Fill DATA into memory
  // to send to UART MODEM Rhea peripheral                    -
  //--------------------------------------------------------------
  for (i=0; i <nb_byte_to_transmit; i++)
    {
      * (ptr_tx_buffer+i) = i+INITIAL_VALUE;
    }
  // select the corresponding request and address according to selected uart 
	if (UartType == UART_MODEM)
		{
		synchro_tx = UART_COM_TX_GDMA_REQ;
		synchro_rx = UART_COM_RX_GDMA_REQ;
		uart_address = MAP_UART_MOD_REG;
		}
	else
		{ // BT uart
		synchro_tx = UART_BT_TX_GDMA_REQ;
		synchro_rx = UART_BT_RX_GDMA_REQ;
		uart_address = MAP_UART_BT_REG;
		}
  
  //------------------------------------------------
  // Configure DMA channel 0 for tx to modem
  //------------------------------------------------
	DMAT_ConfigureRheaMemTransfert(DMA_CHANNEL_0,
												 DMA_SDRAM, (UWORD32) ptr_tx_buffer,
												 DMA_RHEA, (UWORD32) uart_address,
												 DMA_TYPE_8_BITS,    // perif rhea size
												 nb_byte_to_transmit,
												 synchro_tx);
  
  //-----------------------------------------------------------------
  // Configure DMA channel 1 for rx from modem
  //-----------------------------------------------------------------
  
	DMAT_ConfigureRheaMemTransfert(DMA_CHANNEL_1,
												 DMA_RHEA, (UWORD32) uart_address,
												 DMA_SDRAM, (UWORD32) ptr_rx_buffer,
												 DMA_TYPE_8_BITS,    // perif rhea size
												 nb_byte_to_transmit,
												 synchro_rx);

  //----------------------------------------------------
  //  ENABLE CHANNELS 0 & 1
  //----------------------------------------------------
  *end_dma_channel_0=False;
  *end_dma_channel_1=False;
  
  DMA_EnableChannel(DMA_CHANNEL_0); // enable transmit dma channel 
  DMA_EnableChannel(DMA_CHANNEL_1); // enable receive  dma channel 
  
  // write again in SCR register for generating a new Dma_nrequest
  UMOD_InitScr(UARTMOD_SCR_SET_DMA_MODE  , 
		  				UARTMOD_nDMA_REQ_0_in_TX_1_in_RX, 
		  				UARTMOD_THR_IT_NORMAL_MODE, 
		  				UARTMOD_NO_WAKEUP, 
						UARTMOD_MASK_DSR_IT,UARTMOD_Txtriggranu0,
                                    UARTMOD_Rxtriggranu0,
						UartType);
  
  CLKRST_ConfigIdleModule(TIMARM_MODULE_IDLE, SET_IN_IDLE);
  CLKRST_ConfigIdleModule(LCDARM_MODULE_IDLE, SET_IN_IDLE);
  CLKRST_ConfigIdleModule(PERARM_MODULE_IDLE, SET_IN_IDLE);
  CLKRST_ConfigIdleModule(XORPARM_MODULE_IDLE,SET_NOT_IDLE);
  CLKRST_ConfigIdleModule(WDTARM_MODULE_IDLE, SET_IN_IDLE);

// Put arm in idle (wait for interrupt) if interrput isn't yet incoming
if (*end_dma_channel_0 == False)
  CLKRST_SetIdle(IDLE_INT_WKUP);

  
  //---------------------------------------------------
  // WAIT FOR IT DMA of end of Transmission        -
  //---------------------------------------------------
  while (*end_dma_channel_0 ==False) ;
  
 
  //----------------------------------------------------------
  // Wait for IT DMA of Reception                        -
  //----------------------------------------------------------  
  while (*end_dma_channel_1 ==False) ;
  
  
  //--------------------------------------------------------------------
  // Check the data read match the written data        
  //     and that the overflow area is not overwritten                 -
  //-------------------------------------------------------------------- 
  ok=True;
  for (i=0; i <nb_byte_to_transmit; i++)
    {
      if (*(ptr_tx_buffer+i) != *(ptr_rx_buffer+i))
	ok=False;
    }
  // check dma overflow
  if (*(ptr_rx_buffer+nb_byte_to_transmit)!=0x55)
    ok=False;
return(ok);

}

//--------------------------------------------------------------------
// NAME       : UART_TestIrdaSirModeWithDmaUsingSdram
// DESCRIPTION:
//
//  Disable DMA Channel 0 & 1 
//  Configure UART (with external Loop Back TX --> RX)
//  Write overflow data Into destination area
//  Fill DATA to be transfered
//  Enable channel 0 & 1
//  Wait for IT DMA of Sending
//  Disable Transmitter Channel #0
//  Wait for IT DMA of Reception
//  Check the data read match the written data
//  and that the overflow area is not overwritten
//
// PARAMETERS  : Counters of irda & dma IRQs
// RETURN VALUE: RES_OK on success otherwise RES_BAD
//---------------------------------------------------------------------

BOOL UART_TestIrdaSirModeWithDmaUsingSdram(
														  BOOL Enable6_5divider,
														  UWORD32 sdram_src_address,
	                                    	  UWORD32 sdram_dst_address,
				            						  UWORD8 nb_byte_to_transmit,
														  UWORD8 * const irda_irq_count,
														  volatile BOOL * const end_dma_channel_0, 
                                            volatile BOOL * const end_dma_channel_1)

{
  
UWORD32 i;
BOOL ok;
UWORD8 * ptr_tx_buffer;
UWORD8 * ptr_rx_buffer; // one byte more for checking overflow

  
  ptr_tx_buffer = (UWORD8 *) sdram_src_address ;
  ptr_rx_buffer = (UWORD8 *) sdram_dst_address ;
  
  //---------------------------------------------------
  // 0) Initialize UART/IRDA
  //---------------------------------------------------

  UART_TestInitUartIrdaSirMode(nb_byte_to_transmit,
				   UARTTEST_EXTERNAL_LOOPBACK,
				   irda_irq_count,Enable6_5divider); 

  UIRD_Readlsr();
  UIRD_ReadIir();
  
  //----------------------------------------------------
  // 2) CONFIGURE UART fifo trigger
  //----------------------------------------------------
  //DMA MODE FIFO CONTROL REGISTER (FCR) not used , Supplement Control Register set DMA MODE
  //DMA Mode 1 ARM_nDMA_REQ[0] in TX UART IRDA
  // set graanularity of 1 on tx and rx fifo trigger
  UIRD_InitScr(UARTIRDA_SCR_SET_DMA_MODE, 
		   			 UARTIRDA_nDMA_REQ_0_in_TX_1_in_RX, 
		   			 UARTIRDA_THR_IT_NORMAL_MODE, 
		   			 UARTIRDA_NO_WAKEUP, 
						 UARTIRDA_MASK_DSR_IT,
  						 UARTIRDA_TxTriggranu1,
  						 UARTIRDA_RxTriggranu1);

  
  UIRD_ReadIir();

  // set fifo rx and tx trigger of 1, clear fifo
  UIRD_InitFcr(UARTIRDA_ENABLE_FIFOS,
                   UARTIRDA_CLEAR_RX_FIFO,
                   UARTIRDA_CLEAR_TX_FIFO,
                   UARTIRDA_DMA_MODE_0,
                   1,
                   1);

  
  //----------------------------------------------------------
  // init. to check transfer overflow
  //----------------------------------------------------------
  ptr_rx_buffer[nb_byte_to_transmit]=0x55;
  
  //--------------------------------------------------------------
  // Fill DATA into memory to send to UART IRDA
  //--------------------------------------------------------------
  for (i=0; i <nb_byte_to_transmit; i++)
    {
      ptr_tx_buffer[i] = i + INITIAL_VALUE;
    }