📄 uarttest.c
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UartType);
//IER[7:4] can only modified and enabled if EFR[4] is set
UMOD_InitEfr(UARTMOD_RX_NO_FLOW,
UARTMOD_TX_NO_FLOW,
UARTMOD_ENABLE_WRITE_IER,
UARTMOD_DISABLE_SPECIAL_CHAR_DETECT,
UARTMOD_DISABLE_AUTO_RTS,
UARTMOD_DISABLE_AUTO_CTS,
UartType);
//set no Interrupt config & disable sleep mode for config divisor latches
UMOD_InitIer(UARTMOD_MASK_RHR_IT,
UARTMOD_MASK_THR_IT,
UARTMOD_MASK_LINE_STS_IT,
UARTMOD_MASK_MODEM_STS_IT,
UARTMOD_MASK_SLEEP_MODE,
UARTMOD_MASK_XOFF_IT,
UARTMOD_MASK_RTS_IT,
UARTMOD_MASK_CTS_IT,
UartType);
// write in fcr should be done before setting DLH and DLL register
//Used for clear FIFO
UMOD_InitFcr(UARTMOD_DISABLE_FIFOS,
UARTMOD_CLEAR_RX_FIFO,
UARTMOD_CLEAR_TX_FIFO,
UARTMOD_DMA_MODE_0,
UARTMOD_TX_8_SPACES_FIFO_TRIGGER,
UARTMOD_RX_8_CHARS_FIFO_TRIGGER,
UartType);
//--- Program FIFO and DMA mode ---
// FIFO BYPASS in TX and Rx =0, clear FIFO Rx =0 don't care, Clear FIFO tx= 0 don't care,
// DMA mode 0 for used mask dma_reg, trig. TX FIFO , trig.RX FIFO
UMOD_InitFcr(UARTMOD_ENABLE_FIFOS,
UARTMOD_NOCHANGE_RX_FIFO,
UARTMOD_NOCHANGE_TX_FIFO,
UARTMOD_DMA_MODE_0,
UARTMOD_TX_8_SPACES_FIFO_TRIGGER,// theses values correspond to UARTMOD_TX_1_SPACES_FIFO_TRIGGER
UARTMOD_RX_8_CHARS_FIFO_TRIGGER, // and UARTMOD_RX_1_CHARS_FIFO_TRIGGER
UartType);
// enable divisor 6.5 if uart frequency is 12 MHz
if (Enable6_5divider)
UARTMOD_OSC_REG(UartType)=1;
UMOD_InitDivLatch(1,0,UartType);
if (UMOD_ReadDll(UartType) != 0x01 )
{
RES_Set(UARTMOD_DLL_REG_INIT_ERROR);
ok =False;
}
if (UMOD_ReadDlh(UartType) != 0x00 )
{
RES_Set(UARTMOD_DLH_REG_INIT_ERROR);
ok =False;
}
//Disable sleep mode & Mask all modem IT
UMOD_InitIer( UARTMOD_MASK_RHR_IT,
UARTMOD_MASK_THR_IT,
UARTMOD_MASK_LINE_STS_IT,
UARTMOD_MASK_MODEM_STS_IT,
UARTMOD_MASK_SLEEP_MODE,
UARTMOD_MASK_XOFF_IT,
UARTMOD_MASK_RTS_IT,
UARTMOD_MASK_CTS_IT,
UartType);
//--- End sequence for change baud rate ---
// --- Config trame ---
// 8 bits RX and Tx, 1 stop bit, parity trasmit Tx and check Rx, Even= 1, force 0 parity,
//Break control bit =0 , normal mode =0
UMOD_InitLcr(UARTMOD_8BITS_CHAR_LENGTH,
UARTMOD_1_NB_STOP_BITS,
UARTMOD_PARITY_BIT,
UARTMOD_EVEN_PARITY_TYPE,
UARTMOD_NO_BREAK_CONDITION,
UARTMOD_NO_DIVISOR_LATCH_ACCESS,
UartType);
// --- Force signal emulating modem control exchange ---
UMOD_InitMcr(UARTMOD_FAX_MODE_ENABLE,
UARTMOD_OUTPUT_REQUEST_TO_SEND_ENABLE,
UARTMOD_NO_LOOPBACK,
UARTMOD_DISABLE_XON_ANY_FCT,
UARTMOD_DISABLE_TCR_TLR_ACCESS,
UARTMOD_DIV_CLOCK_INPUT_NO_ACTION,
UartType);
UMOD_ReadIir(UartType);
//mode select :start up after config registers DLL,DLH,LCR ..
UMOD_InitMdr1(UARTMOD_UART_SELECT,UartType);
// --- init interrupts ---
//Set no Interrupt config and set disable sleep mode for config divisor latches
UMOD_InitIer(UARTMOD_MASK_RHR_IT,
UARTMOD_MASK_THR_IT,
UARTMOD_MASK_LINE_STS_IT,
UARTMOD_MASK_MODEM_STS_IT,
UARTMOD_MASK_SLEEP_MODE,
UARTMOD_MASK_XOFF_IT,
UARTMOD_MASK_RTS_IT,
UARTMOD_MASK_CTS_IT,
UartType);
// read line status register
//-------------------------------------------
UMOD_ReadLsr(UartType);
return(ok);
}
//------------------------------------------------------------------------
// UART_TestInitUartIrdaSirMode
//------------------------------------------------------------------------
BOOL UART_TestInitUartIrdaSirMode (UWORD16 frame_length,
boolean_t external_loopback,
UWORD8 * const irda_irq_count,
BOOL Enable6_5divider)
{
BOOL ok = True;
*irda_irq_count = 0;
//To be able to update registers
UIRD_Mdr1ResetMode();
//--- Sequence for change baud rate ---
// set register LCR=0xBF for access to EFR register
UIRD_InitLcr(UARTIRDA_8BITS_CHAR_LENGTH,
UARTIRDA_2_NB_STOP_BITS,
UARTIRDA_PARITY_BIT,
UARTIRDA_SPACE_PARITY_TYPE,
UARTIRDA_NO_BREAK_CONDITION,
UARTIRDA_GRANT_DIVISOR_LATCH_ACCESS);
//IER[7:4] can only modified and enabled if EFR[4] is set
UIRD_InitEfr(UARTIRDA_RX_NO_FLOW,
UARTIRDA_TX_NO_FLOW,
UARTIRDA_ENABLE_WRITE_IER,
UARTIRDA_DISABLE_SPECIAL_CHAR_DETECT,
UARTIRDA_DISABLE_AUTO_RTS,
UARTIRDA_DISABLE_AUTO_CTS);
//Set no Interrupt config
UIRD_InitIer(UARTIRDA_MASK_RHR_IT,
UARTIRDA_MASK_THR_IT,
UARTIRDA_MASK_LINE_STS_IT,
UARTIRDA_MASK_MODEM_STS_IT,
UARTIRDA_MASK_SLEEP_MODE,
UARTIRDA_MASK_XOFF_IT,
UARTIRDA_MASK_RTS_IT,
UARTIRDA_MASK_CTS_IT);
if (Enable6_5divider)
UARTIRDA_OSC_REG=1;
// Change Baud Rate
UIRD_InitDivLatch(0x01,0x00); //115200
// UIRD_InitDivLatch(0x0C,0x00); //9600
/*
if (UIRD_ReadDll() != 0x01)
{
RES_Set(UARTIRDA_DLL_INIT_ERROR);
ok = False;
}
if (UIRD_ReadDlh() != 0x00)
{
RES_Set(UARTIRDA_DLH_INIT_ERROR);
ok = False;
}
*/
//--- End sequence for change baud rate ---
// --- Config trame
// 8 bits RX and Tx, 1 stop bit, parity trasmit Tx and check Rx, Even= 1, force 0 parity,
UIRD_InitLcr(UARTIRDA_8BITS_CHAR_LENGTH,
// UARTIRDA_1_NB_STOP_BITS,
UARTIRDA_2_NB_STOP_BITS,
// UARTIRDA_PARITY_BIT,
UARTIRDA_NO_PARITY_BIT,
UARTIRDA_EVEN_PARITY_TYPE,
UARTIRDA_NO_BREAK_CONDITION,
UARTIRDA_DENY_DIVISOR_LATCH_ACCESS);
//Break control bit =0 , normal mode =0
// used for clear FIFO
UIRD_InitFcr(UARTIRDA_DISABLE_FIFOS,
UARTIRDA_CLEAR_RX_FIFO,
UARTIRDA_CLEAR_TX_FIFO,
UARTIRDA_DMA_MODE_0,
UARTIRDA_TX_8_SPACES_FIFO_TRIGGER,
UARTIRDA_RX_8_CHARS_FIFO_TRIGGER);
//--- Program FIFO and DMA mode ---
// FIFO BYPASS in TX and Rx =0, clear FIFO Rx =0 don't care, Clear FIFO tx= 0 don't care,
//DMA mode 0 =1 for used dma_reg mask , trig. TX FIFO , trig.RX FIFO
UIRD_InitFcr(UARTIRDA_ENABLE_FIFOS,
UARTIRDA_NOCHANGE_RX_FIFO,
UARTIRDA_NOCHANGE_TX_FIFO,
UARTIRDA_DMA_MODE_0,
UARTIRDA_TX_8_SPACES_FIFO_TRIGGER,
UARTIRDA_RX_8_CHARS_FIFO_TRIGGER);
// --- Force signal emulating modem control exchange ---
if (external_loopback)
// external loop back
UIRD_InitMcr(UARTIRDA_FAX_MODE_ENABLE,
UARTIRDA_OUTPUT_REQUEST_TO_SEND_ENABLE,
UARTIRDA_NO_LOOPBACK,
UARTIRDA_DISABLE_XON_ANY_FCT,
UARTIRDA_ENABLE_TCR_TLR_ACCESS,
UARTIRDA_DIV_CLOCK_INPUT_NO_ACTION);
else
// internal loop back
UIRD_InitMcr(UARTIRDA_FAX_MODE_ENABLE,
UARTIRDA_OUTPUT_REQUEST_TO_SEND_ENABLE,
UARTIRDA_LOOPBACK,
UARTIRDA_DISABLE_XON_ANY_FCT,
UARTIRDA_ENABLE_TCR_TLR_ACCESS,
UARTIRDA_DIV_CLOCK_INPUT_NO_ACTION);
// very important !! set this register after set clock
// Specific register for the IRDA
// type of start flag 0xff or 0xc0, status reset fifo
UIRD_InitBlr(UARTIRDA_0xFF_BOF_SELECT,
UARTIRDA_RESET_STATUS);
// nb bof = 2
UIRD_InitEblr(2);
UIRD_InitMdr1(UARTIRDA_SLOW_INFRARED_SELECT,
UARTIRDA_DISABLE_SLEEP,
UARTIRDA_ASAP_START,
UARTIRDA_FRAME_LENGTH_METHOD);
UIRD_InitTxflh(frame_length >> 8); // Frame Length of Transmitter (5 MSB)
UIRD_InitTxfll(frame_length & 0x0F); // Frame Length of Transmitter (8 LSB)
UIRD_InitRxflh(frame_length >> 8); // Frame Length of receiver (5 MSB)
UIRD_InitRxfll((frame_length+3) & 0x0F); // Frame Length of receiver + 3 (8 LSB)
/*
// added FH
UIRD_InitAcreg(UARTIRDA_EOT_ON_THR_WRITE,
UARTIRDA_NO_EFFECT_ON_FRAME_ABORTt,
UARTIRDA_SELF_CLEARING_BIT ,
UARTIRDA_NO_TRANSMIT_LONGSTOP,
UARTIRDA_FULL_DUPLEX,
UARTIRDA_SD_MOD_PIN_HIGH,
UARTIRDA_1_6US_PULSE);
*/
// --- Enable interrupts used ---
UIRD_InitIer(UARTIRDA_RHR_IT_ENABLE,
UARTIRDA_THR_IT_ENABLE,
UARTIRDA_LINE_STS_IT_ENABLE,
UARTIRDA_MASK_MODEM_STS_IT,
UARTIRDA_MASK_SLEEP_MODE,
UARTIRDA_MASK_XOFF_IT,
UARTIRDA_RTS_IT_ENABLE,
UARTIRDA_CTS_IT_ENABLE);
// wait INTERRUPT THR empty
do
{
UIRD_ReadIir();
}
while (*irda_irq_count == 0);
return(ok);
}
//--------------------------------------------------------------------
// NAME : UART_TestIrdaBase
// DESCRIPTION:
// Test uart irda in uart mode with loopback
// loopback can be internal or external (via test bench)
// Data are sent by writing in tx register
// Data are read by reading in Rx register
// PARAMETERS :
// nb_byte_to_transmit : number of byte transmitted and received in the test
// external_loopback = True of loopcak is extern (via testbench)
// irda_irq_count = counter of modem irq (should be used in interrupt routine)
// Enable6_5divider = True if enable divider 6.5 for 12 MHZ
// UWORD16 DividerLatch
// RETURN VALUE: RES_OK on success otherwise RES_BAD
//---------------------------------------------------------------------
BOOL UART_TestIrdaBase(UWORD8 nb_byte_to_transmit,
BOOL external_loopback ,
UWORD8 * const irda_irq_count,
BOOL Enable6_5divider,
UWORD16 DividerLatch )
{
//-------------------------------------------------------------------------------
// ----- INIT UART IRDA ----- -
//-------------------------------------------------------------------------------
UART_TestInitIrdaInUartMode(irda_irq_count,external_loopback, Enable6_5divider,DividerLatch);
//-------------------------------------------------------------------------------
// ----- send value ----- -
//-------------------------------------------------------------------------------
UART_TestIrdaSendValue(nb_byte_to_transmit);
//-------------------------------------------------------------------------------
// ----- receive and check results ----- -
//-------------------------------------------------------------------------------
return (UART_TestIrdaInUartModeReceiveAndCheck(nb_byte_to_transmit));
}
//--------------------------------------------------------------------
// NAME : UART_TestIrdaSirModeBase
// DESCRIPTION:
// Test uart irda (in sir mode) in loopback mode wich can be internal or external (via test bench)
// Data are sent by writng in tx register
// Data are read by reading in Rx register
// PARAMETERS :
// nb_byte_to_transmit : number of byte transmitted and received in the test
// external_loopback = True if loopback is extern (via testbench)
// irda_irq_count = counter of irda irq (should be used in interrupt routine)
// Enable6_5divider = True if enable divider 6.5 for 12 MHZ
// RETURN VALUE: True if ok otherwise False
//---------------------------------------------------------------------
BOOL UART_TestIrdaSirModeBase(UWORD8 nb_byte_to_transmit,
boolean_t external_loopback,
UWORD8 * const irda_irq_count,
BOOL Enable6_5divider)
{
UWORD8 index, i;
UWORD16 frame_length;
BOOL ok = True;
UWORD8 receive_values[100];
frame_length = nb_byte_to_transmit; // transmit nb_byte_to_transmit
UART_TestInitUartIrdaSirMode (frame_length,
external_loopback,
irda_irq_count,
Enable6_5divider);
//--------------------------------------
// UART/IRDA SENDS VALUES -
//--------------------------------------
for (i=0; i<nb_byte_to_transmit; i++)
{
UIRD_Send(i + INITIAL_VALUE);
}
// Check Status of irda sender
UIRD_Readlsr();
// wait transmit data is ended, (ie wait until Transmit Hold Register is empty
while( ((UIRD_Readlsr() & 0x80) >> 7) == 0 ) { };
// Check Status of irda receiver
UIRD_Readlsr();
//--------------------------------------------------
// UART IRDA CATCH BACK THE CHARACTERS AND CHECK -
//--------------------------------------------------
index = 0;
while (index < nb_byte_to_transmit)
{
// before read, verify one character is in FIFO receive
if ( UIRD_RxFifoIsNotEmptySirMode() )
{
receive_values[index] = UIRD_Read();
index++;
}
}
for ( i = 0 ; i < nb_byte_to_transmit; i++)
{
if (receive_values[i] != (i + INITIAL_VALUE))
ok=False;
}
return(ok);
}
//--------------------------------------------------------------------
// NAME : UART_TestInitIrdaInUartMode
// DESCRIPTION: init uart irda in uart mode
//---------------------------------------------------------------------
void UART_TestInitIrdaInUartMode(UWORD8 * const irda_irq_count,
BOOL external_loopback,
BOOL Enable6_5divider,
UWORD16 DividerLatch )
{
UWORD8 val;
BOOL ok = True;
//-------------------------------------------------------------------------------
// ----- INIT UART IRDA ----- -
//-------------------------------------------------------------------------------
//init UART MODE
//--- Sequence for change baud rate
// set regiter LCR=0xBF for accsess to EFR register
UIRD_InitLcr(UARTIRDA_8BITS_CHAR_LENGTH,
UARTIRDA_2_NB_STOP_BITS,
UARTIRDA_PARITY_BIT,
UARTIRDA_SPACE_PARITY_TYPE,
UARTIRDA_NO_BREAK_CONDITION,
UARTIRDA_GRANT_DIVISOR_LATCH_ACCESS);
// IER[7:4] can only modified and enabled if EFR[4] is set
UIRD_InitEfr(UARTIRDA_RX_NO_FLOW,
UARTIRDA_TX_NO_FLOW,
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