uarttest.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

/*
===============================================================================
            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
                                                                             
   Property of Texas Instruments 
   For  Unrestricted  Internal  Use  Only 
   Unauthorized reproduction and/or distribution is strictly prohibited.  
   This product is protected under copyright law and trade secret law 
   as an unpublished work.  
   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.
   Filename             : uarttest.c
   Description          : file for the test UART connected to ARM9
   Project              : Perseus
   Author               : Francis Huguenin
===============================================================================
*/

#include "result.h"
#include "gdma.h"
#include "gdmatest.h"
#include "gdma_req.h"
#include "uartmodem.h"
#include "uartirda.h"
#include "uarttest.h"
#include "mapping.h"
#include "clkrst.h"
#include "mux.h"

#define   INITIAL_VALUE        0x41 
#define   UARTIRDA_CE 	       0x7D     // ESC character


BOOL UART_TestModemSignalControl(UARTMOD_UartType_t UartType)
{
UWORD8 line_status;
BOOL ok = False;
// Assumptions : loopback between RTS and CTS ; DCD and DSR
// set RTS 
ok = True;
UMOD_InitMcr(UARTMOD_FAX_MODE_DISABLE, // DCD =0
					UARTMOD_OUTPUT_REQUEST_TO_SEND_DISABLE, //RTS =0
					UARTMOD_NO_LOOPBACK,
					UARTMOD_DISABLE_XON_ANY_FCT,
					UARTMOD_ENABLE_TCR_TLR_ACCESS, 
					UARTMOD_DIV_CLOCK_INPUT_NO_ACTION,
					UartType);

line_status = UMOD_ReadMsr(UartType);
if ((line_status & 0x30) == 0x0)
	{
   RES_Set(TEST_OK);
	}
else
	{
   RES_Set(RES_BAD);
	ok = False;
	}

UMOD_InitMcr(UARTMOD_FAX_MODE_ENABLE, // DCD =1 
					UARTMOD_OUTPUT_REQUEST_TO_SEND_DISABLE, //RTS =0
					UARTMOD_NO_LOOPBACK,
					UARTMOD_DISABLE_XON_ANY_FCT,
					UARTMOD_ENABLE_TCR_TLR_ACCESS, 
					UARTMOD_DIV_CLOCK_INPUT_NO_ACTION,
					UartType);

line_status = UMOD_ReadMsr(UartType);
if ((line_status & 0x30) == 0x20)
	{
   RES_Set(TEST_OK);
	}
else
	{
   RES_Set(RES_BAD);
	ok = False;
	}

UMOD_InitMcr(UARTMOD_FAX_MODE_DISABLE, // DCD =0 
					UARTMOD_OUTPUT_REQUEST_TO_SEND_ENABLE, //RTS =1
					UARTMOD_NO_LOOPBACK,
					UARTMOD_DISABLE_XON_ANY_FCT,
					UARTMOD_ENABLE_TCR_TLR_ACCESS, 
					UARTMOD_DIV_CLOCK_INPUT_NO_ACTION,
					UartType);
line_status = UMOD_ReadMsr(UartType);
if ((line_status & 0x30) == 0x10)
	{
   RES_Set(TEST_OK);
	}
else
	{
   RES_Set(RES_BAD);
	ok = False;
	}

UMOD_InitMcr(UARTMOD_FAX_MODE_ENABLE, // DCD =1
					UARTMOD_OUTPUT_REQUEST_TO_SEND_ENABLE, //RTS =1
					UARTMOD_NO_LOOPBACK,
					UARTMOD_DISABLE_XON_ANY_FCT,
					UARTMOD_ENABLE_TCR_TLR_ACCESS, 
					UARTMOD_DIV_CLOCK_INPUT_NO_ACTION,
					UartType);
line_status = UMOD_ReadMsr(UartType);
if ((line_status & 0x30) == 0x30)
	{
   RES_Set(TEST_OK);
	}
else
	{
   RES_Set(RES_BAD);
	ok = False;
	}
return(ok);
}


BOOL UART_TestIrdaSignalControl(void)
{
UWORD8 line_status;
BOOL ok = False;
// Assumptions : loopback between RTS and CTS ; DCD and DSR
// set RTS 
ok = True;
UIRD_InitMcr(UARTIRDA_FAX_MODE_DISABLE, // DCD =0
					UARTIRDA_OUTPUT_REQUEST_TO_SEND_DISABLE, //RTS =0
					UARTIRDA_NO_LOOPBACK,
					UARTIRDA_DISABLE_XON_ANY_FCT,
					UARTIRDA_ENABLE_TCR_TLR_ACCESS, 
					UARTIRDA_DIV_CLOCK_INPUT_NO_ACTION);

line_status = UIRD_ReadMsr();
if ((line_status & 0x30) == 0x0)
	{
   RES_Set(TEST_OK);
	}
else
	{
   RES_Set(RES_BAD);
	ok = False;
	}

UIRD_InitMcr(UARTIRDA_FAX_MODE_ENABLE, // DCD =1 
					UARTIRDA_OUTPUT_REQUEST_TO_SEND_DISABLE, //RTS =0
					UARTIRDA_NO_LOOPBACK,
					UARTIRDA_DISABLE_XON_ANY_FCT,
					UARTIRDA_ENABLE_TCR_TLR_ACCESS, 
					UARTIRDA_DIV_CLOCK_INPUT_NO_ACTION);

line_status = UIRD_ReadMsr();
if ((line_status & 0x30) == 0x20)
	{
   RES_Set(TEST_OK);
	}
else
	{
   RES_Set(RES_BAD);
	ok = False;
	}

UIRD_InitMcr(UARTIRDA_FAX_MODE_DISABLE, // DCD =0 
					UARTIRDA_OUTPUT_REQUEST_TO_SEND_ENABLE, //RTS =1
					UARTIRDA_NO_LOOPBACK,
					UARTIRDA_DISABLE_XON_ANY_FCT,
					UARTIRDA_ENABLE_TCR_TLR_ACCESS, 
					UARTIRDA_DIV_CLOCK_INPUT_NO_ACTION);
line_status = UIRD_ReadMsr();
if ((line_status & 0x30) == 0x10)
	{
   RES_Set(TEST_OK);
	}
else
	{
   RES_Set(RES_BAD);
	ok = False;
	}

UIRD_InitMcr(UARTIRDA_FAX_MODE_ENABLE, // DCD =1
					UARTIRDA_OUTPUT_REQUEST_TO_SEND_ENABLE, //RTS =1
					UARTIRDA_NO_LOOPBACK,
					UARTIRDA_DISABLE_XON_ANY_FCT,
					UARTIRDA_ENABLE_TCR_TLR_ACCESS, 
					UARTIRDA_DIV_CLOCK_INPUT_NO_ACTION);
line_status = UIRD_ReadMsr();
if ((line_status & 0x30) == 0x30)
	{
   RES_Set(TEST_OK);
	}
else
	{
   RES_Set(RES_BAD);
	ok = False;
	}
return(ok);
}



//--------------------------------------------------------------------
// NAME       : UTST_ModemBase
// DESCRIPTION: 
// Test uart modem in loopback mode wich can be internal or external (via test bench)
// Data are sent by writng in tx register                                     
// Data are read by reading in Rx register                                     
// PARAMETERS  : 
//		nb_byte_to_transmit : number of byte transmitted and received in the test
// 	external_loopback = True of loopback is extern (via testbench)
//    modem_irq_count = counter of modem irq (should be used in interrupt routine)
//    Enable6_5divider = True if enable divider 6.5  
//    DividerLatch
// RETURN VALUE: True if success otherwise False
//---------------------------------------------------------------------
BOOL UTST_ModemBase(UARTMOD_UartType_t UartType,
									UWORD8 nb_byte_to_transmit,
									BOOL external_loopback ,
									UWORD8 * const modem_irq_count, 
									BOOL Enable6_5divider,
									UWORD16 DividerLatch )
{
UWORD8 val;
UWORD32 i;

BOOL ok = True;

//--------------------------------------------------------------------------------
//   ----- INIT UART MODEM-----                                                   
//--------------------------------------------------------------------------------
//--- Sequence for change baud rate ---	
//Set regiter LCR=0xBF for accsess to EFR register
 UMOD_InitLcr(UARTMOD_8BITS_CHAR_LENGTH,
                 UARTMOD_2_NB_STOP_BITS,
                 UARTMOD_PARITY_BIT,
                 UARTMOD_SPACE_PARITY_TYPE, //To check F reygagne
                 UARTMOD_NO_BREAK_CONDITION,
                 UARTMOD_GRANT_DIVISOR_LATCH_ACCESS,
					  UartType);
 
 
 //IER[7:4] can  only modified and enabled if EFR[4] is set  
 UMOD_InitEfr(UARTMOD_RX_NO_FLOW,
		 UARTMOD_TX_NO_FLOW,
		 UARTMOD_ENABLE_WRITE_IER,
		 UARTMOD_DISABLE_SPECIAL_CHAR_DETECT,
		 UARTMOD_DISABLE_AUTO_RTS,
		 UARTMOD_DISABLE_AUTO_CTS,
		UartType);

 
 //set no Interrupt config & disable sleep mode for config divisor latches
 UMOD_InitIer(UARTMOD_MASK_RHR_IT,
		      UARTMOD_MASK_THR_IT,
		      UARTMOD_MASK_LINE_STS_IT,
		      UARTMOD_MASK_MODEM_STS_IT,
		      UARTMOD_MASK_SLEEP_MODE,
		      UARTMOD_MASK_XOFF_IT,
		      UARTMOD_MASK_RTS_IT,
		      UARTMOD_MASK_CTS_IT,
					  UartType);
 
 
 // enable divisor 6.5 if uart frequency is 12 MHz
 if (Enable6_5divider)
     UARTMOD_OSC_REG(UartType)=1;
     
//  set divider latch value
 UMOD_InitDivLatch((DividerLatch&0xFF),((DividerLatch>>8)&0xFF),UartType);
 
 if (UMOD_ReadDll(UartType) != (DividerLatch&0xFF) )
   {
     RES_Set(UARTMOD_DLL_REG_INIT_ERROR);
     ok &= False;
   }
 
 
 if (UMOD_ReadDlh(UartType) != ((DividerLatch>>8)&0xFF) )
   {
     RES_Set(UARTMOD_DLH_REG_INIT_ERROR);
     ok &= False;
   }
 
 //Disable sleep mode & Mask all modem IT
 UMOD_InitIer(UARTMOD_MASK_RHR_IT,
		      UARTMOD_MASK_THR_IT,
		      UARTMOD_MASK_LINE_STS_IT,
		      UARTMOD_MASK_MODEM_STS_IT,
		      UARTMOD_MASK_SLEEP_MODE,
		      UARTMOD_MASK_XOFF_IT,
		      UARTMOD_MASK_RTS_IT,
		      UARTMOD_MASK_CTS_IT,
				UartType);
 
 //---  End sequence for change baud rate ---
 
 
 // --- Config trame  --- 				
 
 // 8 bits RX and Tx, 1 stop bit, parity  trasmit Tx and check Rx, Even= 1, force 0 parity,
 //Break control bit =0 , normal mode =0 */  
 UMOD_InitLcr(UARTMOD_8BITS_CHAR_LENGTH,
                 UARTMOD_1_NB_STOP_BITS,
                 UARTMOD_PARITY_BIT,
                 UARTMOD_EVEN_PARITY_TYPE,
                 UARTMOD_NO_BREAK_CONDITION,
                 UARTMOD_NO_DIVISOR_LATCH_ACCESS,
					  UartType);
 
 // used for clear FIFO
 UMOD_InitFcr(UARTMOD_DISABLE_FIFOS,
                 UARTMOD_CLEAR_RX_FIFO,
                 UARTMOD_CLEAR_TX_FIFO,
                 UARTMOD_DMA_MODE_0,
                 UARTMOD_TX_8_SPACES_FIFO_TRIGGER,
                 UARTMOD_RX_8_CHARS_FIFO_TRIGGER,
					  UartType);

 
 //--- Program FIFO and DMA mode  ---
 //  FIFO BYPASS in TX and Rx =0, clear FIFO Rx =0 don't care, Clear FIFO tx= 0 don't care,
 //DMA mode 0 =1 single character transfers,  trig. TX FIFO don't care , trig.RX FIFO don't care
 UMOD_InitFcr(UARTMOD_ENABLE_FIFOS,
					 UARTMOD_NOCHANGE_RX_FIFO,
					 UARTMOD_NOCHANGE_TX_FIFO,
					 UARTMOD_DMA_MODE_0,
					 UARTMOD_TX_8_SPACES_FIFO_TRIGGER,
					 UARTMOD_RX_8_CHARS_FIFO_TRIGGER,
					 UartType);
                     
 
 
 // --- Force signal emulating modem control exchange ---
 // Force DCD and RTS low
 
 if (external_loopback)
   // external loopback
   UMOD_InitMcr(UARTMOD_FAX_MODE_ENABLE,
		   			UARTMOD_OUTPUT_REQUEST_TO_SEND_ENABLE,
		   			UARTMOD_NO_LOOPBACK,
		   			UARTMOD_DISABLE_XON_ANY_FCT,
		   			UARTMOD_ENABLE_TCR_TLR_ACCESS, 
		   			UARTMOD_DIV_CLOCK_INPUT_NO_ACTION,
						UartType);

 
 else
   // internal loopback
   UMOD_InitMcr(UARTMOD_FAX_MODE_ENABLE,
		   			UARTMOD_OUTPUT_REQUEST_TO_SEND_ENABLE,
		   			UARTMOD_LOOPBACK,
		   			UARTMOD_DISABLE_XON_ANY_FCT,
		   			UARTMOD_ENABLE_TCR_TLR_ACCESS, 
		   			UARTMOD_DIV_CLOCK_INPUT_NO_ACTION,
						UartType);
 
 UMOD_ReadIir(UartType);
 
 *modem_irq_count =0;
 
 
 //mode select :start up after config registers DLL,DLH,LCR ..
 UMOD_InitMdr1(UARTMOD_UART_SELECT,UartType);
 
 // --- Enable interrupts used
 //Set Interrupt config
 UMOD_InitIer(UARTMOD_RHR_IT_ENABLE,
                  UARTMOD_THR_IT_ENABLE,
                  UARTMOD_LINE_STS_IT_ENABLE,
                  UARTMOD_MODEM_STS_IT_ENABLE,
                  UARTMOD_MASK_SLEEP_MODE,
                  UARTMOD_MASK_XOFF_IT,
                  UARTMOD_RTS_IT_ENABLE,
                  UARTMOD_CTS_IT_ENABLE,
						UartType);

 
 
// wait INTERRUPT THR empty
do
   {
   UMOD_ReadIir(UartType);
   }
while ( *modem_irq_count == 0); 
 
 
 //--------------------------------------
 // MODEM SEND VALUE 
 //--------------------------------------
for (i=0; i<nb_byte_to_transmit; i++)
    {
    UMOD_Send(i+ INITIAL_VALUE,UartType);                    
    }
 
//----------------------------------------------
// CHECK STATUS OF MODEM SENDER                -
//----------------------------------------------
UMOD_ReadLsr(UartType);

// wait transmit data is ended, hold and shift register are empty
while ( UMOD_IsTransmitAndHoldRegNotEmpty(UartType) ) ;

//-------------------------------------------
// CHECK STATUS OF MODEM RECEIVER           -
//-------------------------------------------
UMOD_ReadLsr(UartType);


//--------------------------------------------------
//  UART MODEM CATCH BACK THE CHARACTERS AND CHECK -
//--------------------------------------------------
i=0;
ok= True;
while (i < nb_byte_to_transmit)
	{
  	// before read verify one character is in FIFO receive
  	if (UMOD_RxFifoIsNotEmpty(UartType))
   	{
	 	val  = UMOD_Read(UartType);
	 	if (val != (i+ INITIAL_VALUE))
		   ok = False;
	 	i++;
    	}//endif IsnotEmpty
	}//endwhile
 
return(ok) ;

}


//------------------------------------------------------------------------
//	UTST_InitUartModem 
//------------------------------------------------------------------------
BOOL UTST_InitUartModem(UARTMOD_UartType_t UartType,
								BOOL Enable6_5divider)
{
BOOL ok = True;
  
// INIT UART MODEM
//--- Sequence for change baud rate ---	
//Set regiter LCR=0xBF for accsess to EFR register
UMOD_InitLcr(UARTMOD_8BITS_CHAR_LENGTH,
                 UARTMOD_2_NB_STOP_BITS,
                 UARTMOD_PARITY_BIT,
                 UARTMOD_SPACE_PARITY_TYPE, //To check F reygagne
                 UARTMOD_NO_BREAK_CONDITION,
                 UARTMOD_GRANT_DIVISOR_LATCH_ACCESS,